GAA Nanoribbon Gate Oxide Thickness Tuning for Power Scaling
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Solution Overview
Problem
The challenge in forming semiconductor devices with gate-all-around (GAA) transistors is the difficulty in achieving varying gate oxide thicknesses due to the limited spacing between nanoribbons, which hinders the formation of thicker gate oxides required for higher power devices without consuming excessive semiconductor material.
Innovation Solution
The technique involves forming a thicker gate oxide layer by depositing additional silicon and oxidizing it around some nanoribbons, while forming a thinner gate oxide layer over others, allowing for different gate oxide thicknesses on the same substrate, and optionally using a high-k dielectric layer on one but not the other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker gate oxide layer is formed around nanoribbons, then higher power device requirements are met, but excessive semiconductor material is consumed
Solution Approach 1:
The patent applies local quality by forming a thicker gate oxide layer selectively around specific nanoribbons that require higher power handling, while maintaining a thinner gate oxide layer around other nanoribbons. This is achieved through selective deposition processes that target specific regions, allowing each nanoribbon to have the appropriate gate oxide thickness for its intended function, thereby avoiding unnecessary consumption of semiconductor material in regions where it is not needed.
2Adaptability or versatility
If varying gate oxide thicknesses are achieved, then device optimization for different power requirements is enabled, but the limited spacing between nanoribbons makes formation difficult
Solution Approach 1:
The patent segments the gate oxide formation process into distinct stages, allowing different thicknesses to be formed around different nanoribbons. The process involves selective deposition and oxidation steps that can be applied to specific nanoribbon groups, enabling independent control of gate oxide thickness for each segment of the device array, thus overcoming the limitations imposed by tight spacing.
Solution Approach 2:
The patent introduces an additional dimension of control by using vertical stacking of deposition layers and selective oxidation processes. Instead of relying solely on horizontal spacing between nanoribbons, the solution exploits the vertical dimension through multi-layer deposition and selective etching/oxidation, allowing thickness variation without requiring increased lateral spacing.
3Power
If additional silicon is deposited and oxidized to form thicker gate oxide, then higher power applications are supported, but channel area is lost
Solution Approach 1:
The patent applies local quality by forming thicker gate oxide layers only around specific nanoribbons designated for higher power applications, while maintaining thinner gate oxide layers around nanoribbons where channel area is prioritized. This selective approach ensures that channel area is preserved in regions where it is most critical, while still enabling higher power handling in specific devices that require it.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the fabrication of GAA semiconductor devices with distinct gate oxide thicknesses, optimizing the use of semiconductor material and supporting higher power applications without significant loss of channel area.
Implementation Method 1
depositing additional silicon and oxidizing it around some nanoribbons
Implementation Method 2
oxidizing it around some nanoribbons
Implementation Method 3
a high-k dielectric layer may also be formed over the first and second gate oxide layers
Data Source
AI summary
Techniques are provided herein to form semiconductor devices having different gate oxide thicknesses. A first semiconductor device includes a first gate structure around a first plurality of semiconductor nanoribbons and a second semiconductor device includes a second gate structure around a second plurality of semiconductor nanoribbons. The first gate structure includes at least a first gate oxide layer and a first gate electrode, and the second gate structure includes at least a second gate oxide layer and a second gate electrode. The first gate oxide layer is thicker than the second gate oxide layer. A high-k dielectric layer may be formed over the first and second gate oxide layers or may be formed over the second gate oxide layer, but not over the first gate oxide layer.