GAA Gate Metal Recess Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As the semiconductor industry advances to nanometer technology process nodes, challenges in fabrication and design lead to the need for three-dimensional transistor designs like the gate-all-around (GAA) FET, which requires efficient manufacturing methods to achieve higher device density, performance, and lower costs.
Innovation Solution
The method involves depositing an epitaxial stack over a semiconductor substrate, patterning it to form semiconductor fins, removing sacrificial layers, forming gate dielectric and metal layers, and creating a dielectric feature in the gate metal layer to reduce gate-to-source/drain capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar transistor designs are used, then manufacturing is simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from planar two-dimensional transistor designs to three-dimensional gate-all-around structures. The gate electrode completely surrounds the channel region in three dimensions, enabling fuller depletion and better control. This dimensional change allows higher device density while maintaining manufacturability through systematic process steps including epitaxial growth, selective removal, and conformal deposition.
Solution Approach 2:
The gate electrode is nested around the channel region in a gate-all-around configuration, with the gate dielectric layer nested between them. This nested structure enables complete surrounding of the channel, achieving fuller depletion and reduced short-channel effects while maintaining a structured manufacturing approach.
2Object-affected harmful factors
If gate-all-around structures are formed without gate recesses, then manufacturing is simpler, but gate-to-source/drain capacitance is higher
Solution Approach 1:
The gate structure is segmented into distinct regions: the gate electrode, gate dielectric layer, and recess portions. By creating recesses in the gate electrode above the source and drain regions, the patent segments the gate structure to reduce overlapping capacitance while maintaining the overall gate-all-around functionality. This segmentation is achieved through selective etching and conformal deposition steps.
Solution Approach 2:
The patent introduces vertical recesses in the gate electrode structure, transitioning from a flat continuous gate to a three-dimensional segmented structure. These recesses reduce the gate-to-source/drain capacitance by minimizing the overlapping area while maintaining gate control, and are formed through additional etching and deposition steps that add controlled complexity.
3Manufacturing precision
If epitaxial growth is used to form channel layers, then material composition control is improved, but process time and complexity increase
Solution Approach 1:
The patent performs preliminary epitaxial growth to form alternating semiconductor layers with different compositions before any patterning or removal steps. This preliminary action establishes the precise material composition and layer structure early in the process, enabling subsequent selective removal and gate formation without compromising material quality. The epitaxial growth is performed in-situ with precise control over composition and thickness.
Solution Approach 2:
The patent utilizes epitaxial growth parameters such as temperature, pressure, and gas flow rates to precisely control the composition and properties of alternating semiconductor layers. By adjusting these parameters during in-situ growth, the patent achieves accurate material composition control while integrating the process efficiently into the overall fabrication sequence, minimizing total process time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of integrated circuit devices with reduced gate-to-source/drain capacitance, improved performance, and increased device density, addressing the challenges of advanced semiconductor technology.
Implementation Method 1
depositing an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack includes a plurality of first and second semiconductor layers alternatively arranged over the semiconductor substrate
Data Source
AI summary
A method for manufacturing an integrated circuit device is provided. The method includes depositing an epitaxial stack comprising alternative first and second semiconductor layers over a semiconductor substrate; patterning the epitaxial stack to form first and second semiconductor fins; removing the first semiconductor layers in the first and second semiconductor fins, while leaving a first set of the second semiconductor layers in the first semiconductor fin and a second set of the second semiconductor layers in the second semiconductor fin; forming a gate dielectric layer around the first and second sets of the second semiconductor layers; depositing a gate metal layer over the gate dielectric layer; etching a recess in the gate metal layer and between the first and second sets of the second semiconductor layers, wherein the gate metal layer has a first portion below the recess; and forming a dielectric feature in the recess.