Gate Spacer Treatment for GAA Gate Oxide Thickness Control
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Solution Overview
Problem
The presence of dangling bonds on the gate spacer surfaces during the fabrication of Gate-All-Around (GAA) transistors leads to an increase in the thickness of the interfacial layer, which results in higher channel resistance and reduced channel current, causing process variation and performance issues.
Innovation Solution
A method involving ion implantation and anneal processes is employed to neutralize surface dangling bonds on the gate spacer, followed by forming a capping layer and removing the dummy gate stack, thereby preventing the thickening of the interfacial layer and straining the channel layers for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation and anneal processes are employed to neutralize dangling bonds on gate spacer surfaces, then the interfacial layer thickness is reduced and channel resistance decreases, but the process complexity and manufacturing steps increase
Solution Approach 1:
The ion implantation process is performed at a predetermined stage before interfacial layer formation to pre-neutralize dangling bonds on the gate spacer surface. This preliminary action prevents the formation of excessive interfacial layer thickness that would otherwise occur during subsequent oxidation processes, thereby achieving precise thickness control without requiring additional corrective steps.
Solution Approach 2:
The invention changes the physical and chemical parameters of the gate spacer surface by implanting ions (such as nitrogen or carbon) at controlled energies and doses. This parameter change modifies the surface chemistry to reduce dangling bonds, which directly controls the interfacial layer growth characteristics and achieves the desired thickness precision.
2Reliability
If the interfacial layer thickness is reduced through ion implantation, then channel resistance decreases and on-state current enhances, but the process time and energy consumption increase
Solution Approach 1:
The ion implantation process is integrated into the continuous fabrication flow without interrupting the overall process sequence. The anneal step that follows immediately activates the implanted ions and completes the dangling bond neutralization, ensuring continuous useful action that achieves performance improvement without unnecessary energy-wasting interruptions or rework cycles.
Solution Approach 2:
The anneal process induces a phase transition in the implanted ions, transforming them from a metastable state to a stable configuration that effectively neutralizes dangling bonds. This phase transition occurs at controlled temperatures and times, achieving the desired electrical performance improvement with optimized energy input rather than excessive heating.
3Productivity
If multiple processing steps including ion implantation and annealing are added, then the effective gate oxide thickness is reduced and carrier mobility increases, but the production cycle time extends
Solution Approach 1:
The ion implantation and anneal processes are merged with existing fabrication steps rather than being added as separate standalone operations. The ion implantation is performed using the same equipment infrastructure as other doping processes, and the anneal step is combined with subsequent thermal processing steps, thereby achieving carrier mobility improvement without proportionally extending the production cycle time.
Solution Approach 2:
The ion implantation process serves multiple functions simultaneously: it neutralizes dangling bonds on the gate spacer surface, controls interfacial layer thickness, and prepares the surface for optimal interfacial layer formation. This multi-functionality reduces the need for separate dedicated process steps, thereby maintaining productivity while achieving the desired effective gate oxide thickness reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces the effective gate oxide thickness, enhances on-state current, and decreases channel resistance, while also inducing tensile stress in the ILD layer to increase carrier mobility in GAA transistors.
Implementation Method 1
performing an ion implantation process to the structure
Implementation Method 2
a micro second annealing process is performed
Data Source
AI summary
A method according to the present disclosure includes receiving a structure that includes a source/drain feature sandwiched between a first channel region and a second channel region, a first dummy gate stack over the first channel region, a first gate spacer extending along a sidewall of the first dummy gate stack, a second dummy gate stack over the second channel region, a second gate spacer extending along a sidewall of the second dummy gate stack, and an interlayer dielectric (ILD) layer over the source/drain feature and disposed between the first gate spacer and the second gate spacer, selectively recessing the ILD layer to form a top recess, after the selectively recessing, performing an ion implantation process to the structure, and after the ion implantation process, forming a capping layer in the top recess.