Gate-All-Around Nanostructure Gate Stack for Full Channel Depletion

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Solution Overview

Problem

Existing gate-all-around (GAA) FET devices face challenges in achieving full depletion of the channel region and controlling current due to the uncontrolled bottom part of the channel region, leading to short-channel effects and sub-threshold current swing issues.

Innovation Solution

A method for forming a multi-gate semiconductor device involving the use of a dummy gate structure, spacers, and a gate dielectric layer to surround the channel region, ensuring complete gate control by patterning the GAA structure using photolithography and self-aligned processes, and replacing the dummy gate with a high-K dielectric layer and metal gate electrode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a gate electrode is placed adjacent to three side surfaces of a channel region (FinFET configuration), then the transistor achieves three-gate control, but the bottom part of the channel region remains far from the gate electrode and is not under close gate control

Engineering Contradiction:
Improvegate controlVSAvoidchannel depletion
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent transitions from a planar gate structure to a three-dimensional gate-all-around structure that wraps around the channel region in multiple dimensions. The gate electrode is positioned on all four side surfaces of the channel region, adding vertical and lateral dimensional control to achieve complete surround control, eliminating the uncontrolled bottom region present in FinFET designs.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The gate structure is nested around the channel region, with the gate electrode completely surrounding the channel on all sides. This nested configuration allows the gate to control the channel from all directions, achieving full depletion and eliminating short-channel effects that occur when the gate cannot reach certain regions of the channel.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Device complexity

If the bottom part of the channel region is not under close gate control, then the device structure is simpler, but short-channel effects and sub-threshold current swing issues occur

Engineering Contradiction:
Improvegate structureVSAvoidcurrent control
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements a gate-all-around structure that extends control to all four lateral surfaces of the channel region, adding dimensional coverage to achieve complete gate control. This multi-dimensional approach ensures that the gate electrode is in close proximity to all parts of the channel, eliminating short-channel effects and improving current control without excessive structural complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250311279A1Multi-gate semiconductor device
Publication Date: 2025.10.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250311279A1 patent drawing
  • US20250311279A1 patent drawing
  • US20250311279A1 patent drawing

AI summary

A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, and a gate conductive structure over the gate dielectric layer. The gate conductive structure includes a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer, and a top surface of the second metal layer is higher than a top surface of the first metal layer.