Gate-All-Around Gate Stack for Threshold Voltage Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high reliability, high performance, and multiple functions while maintaining small size and low cost, particularly in gate-all-around type transistors.
Innovation Solution
A method of fabricating semiconductor devices involves forming sacrificial patterns and semiconductor patterns alternately stacked on a substrate, followed by depositing dielectric and work function adjusting patterns in an in-situ manner to create gate electrodes, with specific materials and structures to enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-all-around type transistor structure is implemented to improve device performance and integration density, then electrical characteristics and integration density are improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure is segmented into multiple components: gate electrode, first gate insulating layer, second gate insulating layer, and work function adjusting patterns. This segmentation allows each component to be optimized independently for electrical performance while simplifying the overall manufacturing process through modular fabrication steps.
Solution Approach 2:
Sacrificial patterns are formed in advance before the gate structure fabrication. These sacrificial patterns serve as templates that guide the subsequent formation of gate spacers and gate electrodes, pre-establishing the spatial configuration needed for the gate-all-around structure and reducing complexity in later steps.
2Adaptability or versatility
If multiple work function adjusting patterns are deposited to achieve different threshold voltages, then device functionality and adaptability are improved, but process complexity increases
Solution Approach 1:
Different work function adjusting patterns are applied to different regions: first work function adjusting pattern for NMOS transistors and second work function adjusting pattern for PMOS transistors. This local differentiation enables independent threshold voltage optimization for each transistor type without affecting the other, achieving high adaptability through region-specific material properties.
Solution Approach 2:
The gate structure incorporates multiple insulating layers and work function adjusting patterns that serve dual purposes: electrical insulation and work function adjustment. The first and second gate insulating layers provide both isolation and contribute to threshold voltage control, reducing the need for separate dedicated adjustment layers and simplifying the overall process.
3Reliability
If sacrificial patterns and semiconductor patterns are alternately stacked to form channel patterns, then transistor performance is improved, but fabrication difficulty increases
Solution Approach 1:
Sacrificial patterns are formed in advance as templates before the actual channel pattern fabrication. These pre-formed sacrificial structures guide the deposition and patterning of semiconductor layers, ensuring precise alignment and positioning of the channel region without requiring complex real-time alignment procedures during manufacturing.
Solution Approach 2:
Gate spacers serve as intermediary structures that are formed between the sacrificial patterns and the final gate electrode. These spacers act as mediators that define the gate region boundaries and provide a foundation for the gate electrode formation, simplifying the transition from sacrificial pattern removal to gate structure assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the electrical performance and reliability of semiconductor devices by optimizing the gate structure, allowing for different threshold voltages and reduced resistance, thereby enhancing device functionality.
Implementation Method 1
sequentially depositing a dielectric layer, a first work function adjusting pattern, and a second work function adjusting pattern
Implementation Method 2
sequentially depositing a dielectric layer, a first work function adjusting pattern, and a second work function adjusting pattern
Data Source
AI summary
A semiconductor device may include a channel pattern stacked on a substrate and a gate electrode on the substrate. The channel pattern includes semiconductor patterns. The gate electrode extends to cross the channel pattern. The gate electrode may include dielectric layers, first work function adjusting patterns, and second work function adjusting patterns. The dielectric layers may enclose the semiconductor patterns, respectively. The first work function adjusting patterns may enclose the dielectric layers, respectively, and the second work function adjusting patterns may enclose the first work function adjusting patterns, respectively. The first work function adjusting patterns may be formed of an aluminum-containing material, and each corresponding one of the first work function adjusting patterns may be in contact with a corresponding one of the second work function adjusting patterns enclosing the corresponding one of the first work function adjusting patterns.