GAA Gate Work Function Mismatch for Scaled Channel Pitch
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Solution Overview
Problem
Vertical scaling of Gate All Around (GAA) devices leads to increased effective capacitance and performance degradation, particularly in device speed, due to challenges in designing and fabricating GAA metal structures with different threshold voltages, especially when scaling down the pitch between stacked semiconductor channel layers.
Innovation Solution
Implementing a GAA transistor structure with a work function mismatch between inner and outer gates, where the inner gates are thinner than the outer gates, allowing for a scalable design with a thickness ratio of 4:1 or higher, and a work function difference of ±250 meV, which simplifies the fabrication process and maintains device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the pitch between stacked semiconductor channel layers is scaled down to improve device performance, then device speed is enhanced due to reduced effective capacitance, but the space between channel layers becomes more confined making fabrication more difficult
Solution Approach 1:
The patent applies local quality by differentiating the gate structure into two distinct regions: inner gates with a first work function (4.5-4.8 eV) and outer gates with a second work function (4.0-4.3 eV). This local differentiation allows each gate region to be optimized independently - inner gates for precise threshold voltage control and outer gates for enhanced channel control - thereby enabling pitch scaling while maintaining fabrication feasibility through specialized processing for each gate type.
Solution Approach 2:
The gate structure is segmented into inner gates and outer gates with different work functions, allowing independent optimization of each segment. The inner gates (thickness: 1-3 nm) provide precise threshold voltage control while the outer gates (thickness: 3-5 nm) provide enhanced channel control. This segmentation enables the pitch to be scaled down while maintaining fabrication feasibility through specialized processing for each gate type.
2Adaptability or versatility
If different variants of GAA devices with different threshold voltages are fabricated, then multi-Vt-options are achieved, but the design and fabrication process becomes more complex
Solution Approach 1:
The patent enables multi-Vt-options through local quality differentiation by providing inner gates with a first work function (4.5-4.8 eV) and outer gates with a second work function (4.0-4.3 eV). This local differentiation allows independent threshold voltage tuning for each gate type, enabling diverse device variants (e.g., low-Vt, medium-Vt, high-Vt) to be fabricated using the same base structure with adjusted gate ratios or thicknesses, thereby reducing overall design complexity.
Solution Approach 2:
The patent provides dynamic adaptability for multi-Vt-options by allowing the threshold voltage to be tuned through variable ratios of inner gate to outer gate areas, or through adjustable gate thicknesses (inner: 1-3 nm, outer: 3-5 nm). This dynamic configuration enables a single fabrication process to produce multiple device variants with different threshold voltages, reducing the need for completely separate design and fabrication flows.
3Speed
If the pitch between channel layers is scaled down, then effective capacitance is reduced and performance is enhanced, but the gate oxide thickness requirement for I/O devices becomes harder to meet
Solution Approach 1:
The segmented gate structure with inner and outer gates allows independent optimization of the gate oxide regions. The inner gate oxide can be optimized for thin-pitch logic devices while the outer gate oxide can be thickened for I/O devices requiring higher breakdown voltage. This segmentation enables pitch scaling while maintaining the ability to provide thicker gate oxide where required for I/O applications.
Data Source
AI summary
The present disclosure relates to a gate all around (GAA) device made based on a GAA transistor structure that comprises a stack of multiple semiconductor channel layers and one or more first gate layers alternatingly arranged along a first direction. Each channel layer is encapsulated by a gate dielectric layer, and each first gate layer is arranged between two channel layers following another. The GAA transistor structure further comprises two second gate layers sandwiching the stack in a second direction and connected to the first gate layers. Each first gate layer is made of a first work function metal structure and each second gate layer is made of a second work function metal structure that is different from the first work function metal structure. Each first gate layer has a first thickness and each second gate layer has a second thickness larger than the first thickness.