GAA FET Inner Spacer Geometry for Uniform Nanowire Release
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Solution Overview
Problem
In the fabrication of gate-all-around (GAA) FETs, controlling lateral etching during the release of nanowires and forming uniform inner spacers is challenging, leading to issues with gate control and increased channel resistance, particularly in larger wafers like 12-inch wafers.
Innovation Solution
The use of a wedge-shaped or triangular cross-section inner spacer defined by a semiconductor crystal (111) facet, which provides a self-limited etch stop property, enhances uniformity and improves gate control by allowing more space for gate dielectric and electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lateral etching is used to release nanowires, then nanowire release is achieved, but lateral etching uniformity deteriorates and inner spacer formation becomes non-uniform
Solution Approach 1:
The patent applies preliminary action by forming the inner spacer structure before the nanowire release etching step. The sacrificial layer is patterned with a specific geometry (wider at top, narrower at bottom) that pre-determines the final inner spacer dimensions. This preliminary structuring ensures that when the release etching occurs, the inner spacer is already in place to provide uniform gate control, eliminating the need for precise lateral etching control.
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary element that mediates between the gate structure and the channel region. This sacrificial layer is selectively removed to release the nanowires while the inner spacer (formed on the sacrificial layer) remains to provide structural support and electrical isolation. The intermediary sacrificial layer enables controlled nanowire release without compromising inner spacer uniformity.
2Productivity
If larger wafer sizes (12-inch) are used to increase productivity, then manufacturing capacity improves, but maintaining fabrication uniformity across the wafer becomes more difficult
Solution Approach 1:
The patent segments the fabrication process into distinct modular steps: forming the sacrificial layer with specific geometry, forming the inner spacer on the sacrificial layer, patternning the gate electrode, and selectively removing the sacrificial layer. This segmentation allows each step to be optimized and controlled independently, ensuring uniform results across large 12-inch wafers. The modular approach enables better process control and reduces variability.
Solution Approach 2:
The patent employs parameter changes by utilizing the vertical geometry of the sacrificial layer (wider at top, narrower at bottom) to control the final inner spacer dimensions. By changing the geometric parameters of the sacrificial layer structure, the process achieves self-aligned formation of uniform inner spacers across the entire wafer surface, maintaining fabrication precision even at large wafer sizes.
3Reliability
If the gate structure is formed closer to the channel to improve gate control, then gate control improves, but space for gate dielectric and electrode formation becomes insufficient
Solution Approach 1:
The patent resolves the space conflict by transitioning to a three-dimensional inner spacer structure with varying cross-sectional dimensions. The inner spacer is wider at the top (providing space for gate dielectric and electrode) and narrower at the bottom (maintaining close gate-to-channel control). This dimensional variation in the vertical direction allows simultaneous achievement of good gate control and sufficient space for gate structure formation.
Solution Approach 2:
The patent applies the nested doll principle by placing the gate dielectric layer and gate electrode layer inside and around the inner spacer structure. The inner spacer serves as a containing structure that defines the space for the gate components while maintaining close proximity to the channel. This nesting arrangement maximizes space utilization and achieves both gate control and structural requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates better gate control and reduces channel resistance, ensuring consistent fabrication across larger wafers by providing a uniform structure from the channel bottom to top.
Implementation Method 1
The use of a wedge-shaped or triangular cross-section inner spacer defined by a semiconductor crystal (111) facet, which provides a self-limited etch stop property
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.