Nanowire Stack GAA Inner Spacer for Low-Resistance Source/Drain Junctions
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Solution Overview
Problem
CMOS transistors face short-channel effects due to shorter gate lengths, compromising current control, and existing solutions like FinFETs and gate-all-around FETs require improved electrostatic control and low resistance junctions between source/drain and nanowire channel regions.
Innovation Solution
A gate-all-around FET device is developed with a stack of silicon and silicon germanium nanowire strips, where sacrificial strips are selectively recessed to form inner spacers, ensuring exposed edge surfaces for Ohmic junctions with source/drain regions, and a replacement gate structure is formed to wrap around the nanowire channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate length is shortened to increase switching speed, then switching speed is improved, but short-channel effects worsen and compromise current control
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire channels with gate-all-around configuration. The gate wraps completely around the nanowire channel in four sides (top, bottom, and two sidewalls), providing 360-degree electrostatic control. This dimensional change from surface gate to surrounded gate enables effective current control in short-channel devices by eliminating the short-channel effects that plague planar transistors.
Solution Approach 2:
The gate structure is nested around the nanowire channel, with the gate electrode completely surrounding the channel region. This nested configuration allows the gate to control current flow from multiple directions simultaneously, providing superior electrostatic control compared to conventional top-gate configurations. The inner spacer is also nested within the structure, positioned between the gate and source/drain regions.
2Reliability
If inner spacer is formed covering the nanowire edge surfaces, then electrostatic control is improved, but junction resistance increases due to dielectric coverage
Solution Approach 1:
The inner spacer is designed with non-uniform coverage: it covers the lower portion of the nanowire edge surfaces to provide electrostatic control and prevent shorting, but deliberately leaves the upper edge surfaces exposed. This local quality differentiation allows the spacer to fulfill its electrostatic control function while maintaining low resistance Ohmic junctions between source/drain and channel through the exposed edge surfaces.
Solution Approach 2:
Instead of completely covering the nanowire edge surfaces with dielectric material, the inner spacer applies partial coverage only where needed for electrostatic control. This partial action approach provides sufficient field control to prevent short-channel effects while avoiding excessive dielectric coverage that would increase junction resistance and degrade contact quality.
3Reliability
If replacement gate process is used to achieve gate-all-around configuration, then electrostatic control is enhanced, but device complexity increases
Solution Approach 1:
The fabrication process uses preliminary sacrificial structures (dummy gates and sacrificial nanowires) that are formed first, then selectively removed to create the final gate-all-around configuration. The inner spacer is formed early in the process on the sacrificial structures, then remains in place after sacrificial material removal to provide the necessary electrostatic control. This preliminary action approach simplifies the overall process by using self-aligned formation steps rather than requiring complex direct patterning of the final gate structure.
Solution Approach 2:
Sacrificial structures serve as intermediary elements during fabrication. Dummy gates and sacrificial nanowires are temporarily formed to define the final gate and channel positions, then selectively removed. The inner spacer acts as an intermediary that remains from the sacrificial structure formation step and provides continuous electrostatic control throughout the process, mediating between the temporary sacrificial structures and the final device configuration.
Data Source
AI summary
The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.