GAA Semiconductor Memory Buffer Patterns for Interference Control
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Solution Overview
Problem
Current semiconductor devices with three-dimensional memory cells face challenges in improving operational reliability and efficiency due to limitations in the design of conductive patterns surrounding the channel layer, which affect the speed of erase and program operations and lead to interference between adjacent memory cells.
Innovation Solution
A semiconductor device with a Gate All Around (GAA) structure is developed, featuring a conductive pattern surrounding a channel layer, interlayer insulating layers, buffer patterns with densified areas, and a blocking insulating pattern, where the buffer patterns are densified to control the effective gate length and reduce interference, and the conductive pattern is shaped to optimize operational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional conductive patterns are used surrounding the channel layer, then the device structure is simpler, but the operational reliability and efficiency deteriorate due to interference between adjacent memory cells and slower erase/program speeds
Solution Approach 1:
The conductive pattern is segmented into multiple distinct layers (first conductive pattern layer, second conductive pattern layer, third conductive pattern layer) with different materials and functions. This segmentation allows each layer to be optimized independently for its specific role, reducing interference between adjacent memory cells while improving operational reliability.
Solution Approach 2:
Different portions of the conductive pattern structure are assigned different materials and properties: the first conductive pattern layer uses a first material with specific electrical characteristics, the second layer uses a second material optimized for charge storage, and the third layer uses a third material for electrical connection. This local quality differentiation resolves the contradiction by providing tailored properties in each region.
2Productivity
If the conductive pattern is optimized for faster erase and program operations, then the operational speed improves, but the device complexity increases due to additional layers and materials
Solution Approach 1:
The multi-layer conductive pattern structure enables dynamic control of electrical characteristics during different operational phases. The first conductive pattern layer provides rapid charge injection for fast programming, while the second and third layers facilitate efficient charge removal for fast erasing, achieving high-speed operations through coordinated action of multiple layers.
Solution Approach 2:
The conductive pattern employs composite material construction with at least three different materials in the conductive pattern layers. This composite structure combines the advantages of different materials to achieve both fast erase/program speeds and reduced interference, resolving the contradiction between speed and complexity.
3Manufacturing precision
If buffer patterns without densified areas are used, then the manufacturing process is simpler, but the effective gate length control and interference reduction are insufficient
Solution Approach 1:
The buffer pattern is pre-formed with a densified area before the conductive pattern layers are deposited. This preliminary densification action establishes precise boundaries and effective gate length control upfront, preventing interference issues before they occur and simplifying subsequent manufacturing steps.
Solution Approach 2:
The buffer pattern's physical and electrical parameters are changed through the formation of a densified area, altering its density, conductivity, and dimensional characteristics. This parameter change enables precise effective gate length control and interference reduction while maintaining manufacturability through standard fabrication techniques.
Data Source
AI summary
Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.