GAA Nanosheet Gate Structure for High-Current Dense Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing integration density and improving current conduction in transistor devices, particularly in achieving high current levels while maintaining device efficiency.
Innovation Solution
The development of a gate-all-around (GAA) field-effect-transistor (FET) device with an active gate structure that wraps around multiple stacks of channel layers, connected by laterally extending portions of the cladding layer, allowing for simultaneous conduction across multiple channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but the current conduction capability of individual transistors decreases
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional non-planar structures including fins and nanosheets. By stacking multiple thin semiconductor layers vertically to form nanosheet channels, the effective channel area increases in the vertical dimension while maintaining small lateral feature sizes, thereby achieving both high integration density and sufficient current conduction capability
Solution Approach 2:
The gate structure completely surrounds the channel structure in three dimensions, with the gate wrapping around the nanosheet channels from top, bottom, and sidewalls. This nested configuration maximizes the gate's control over the channel while maintaining a compact footprint, enabling high integration density without sacrificing transistor performance
2Power
If planar transistor structures are used, then manufacturing is simpler, but current conduction levels are insufficient for high-performance applications
Solution Approach 1:
The channel is divided into multiple thin semiconductor layers stacked vertically to form separate nanosheet channels, with each layer acting as an independent conduction path. This segmentation increases the total channel area and current conduction capability while maintaining compatibility with existing planar manufacturing processes through sequential layer formation
Solution Approach 2:
The invention moves from two-dimensional planar channels to three-dimensional vertically-stacked nanosheet channels. The non-planar gate structure wraps around these vertical channels, providing all-around control. This dimensional transition enables superior current conduction and gate control without requiring completely new manufacturing paradigms
3Power
If gate structures wrap around multiple channel stacks, then current conduction increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the multiple semiconductor layers and isolation structures in a predetermined sequence before forming the gate structure. By establishing the vertical stack geometry and lateral positioning of nanosheets relative to isolation regions in advance, the subsequent gate formation process inherits this pre-established alignment, reducing the precision demands on the final wrapping step
Solution Approach 2:
Isolation structures are introduced as intermediary elements that define the lateral boundaries and positioning of the nanosheet channels. These isolation regions serve as reference features during fabrication, enabling precise alignment of the gate material as it is deposited to wrap around the channel stacks. The intermediary isolation structures mediate between the channel formation and gate wrapping processes
Data Source
AI summary
A semiconductor device includes a first plurality of channel layers. The first plurality of channel layers extend along a first direction. The semiconductor device includes a second plurality of channel layers. The second plurality of channel layers also extend along the first direction. The semiconductor de123329-vice includes a first dielectric fin structure that also extends along the first direction. The semiconductor device includes a first gate structure that extends along a second direction. The first gate structure comprises a first portion that wraps around each of the first plurality of channel layers and a second portion that wraps around each of the second plurality of channel layers. The first dielectric fin structure separates the first and second portions from each other. The first gate structure comprises a third portion that connects the first and second portions to each other and is vertically disposed below the first dielectric fin structure.