Low-k Isolation Layer for GAA Nanowire Leakage Control
Solution Overview
Problem
Gate-all-around (GAA) semiconductor devices face challenges in preventing electrical leakage from nanowires into the substrate, particularly due to the increased capacitance of high-k dielectric materials between nanowires closest to the substrate.
Innovation Solution
The implementation of a low dielectric constant (low-k) material between the substrate and the first GAA semiconductor body, allowing for selective etching and replacement of the first sacrificial layer with a low-k dielectric material to electrically insulate the bottom nanowire from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric material is used between nanowires and substrate, then gate control is improved, but off-state leakage current increases
Solution Approach 1:
The dielectric structure is segmented into multiple layers: a first dielectric layer with low-k material directly contacting the substrate, and a second dielectric layer with high-k material positioned between the nanowire and the first dielectric layer. This segmentation allows the low-k layer to block leakage while the high-k layer provides gate control.
Solution Approach 2:
Different dielectric materials are positioned at different locations to serve different functions: low-k dielectric material is placed where leakage blocking is needed (at the substrate interface), while high-k dielectric material is placed where electric field enhancement is needed (between nanowire and gate).
2Reliability
If high-k dielectric material is placed between nanowire and substrate, then electrical insulation is improved, but capacitance increases causing leakage
Solution Approach 1:
The dielectric structure is divided into two functional segments: a low-k dielectric layer for leakage blocking with minimal capacitance, and a high-k dielectric layer for electrical insulation positioned away from the substrate. This segmentation reduces overall capacitance while maintaining insulation.
Solution Approach 2:
The low-k dielectric layer acts as an intermediary between the high-k dielectric layer and the substrate, providing a low-capacitance path that blocks leakage current while allowing the high-k layer to maintain electrical insulation without excessive capacitance.
3Object-generated harmful factors
If low-k dielectric material is used between substrate and nanowire, then leakage current is reduced, but gate control is weakened
Solution Approach 1:
The dielectric structure uses local quality differentiation: low-k material is placed specifically at the substrate interface where leakage blocking is critical, while high-k material is placed in the region where gate control is needed, ensuring each location has the optimal material property for its function.
Solution Approach 2:
The dielectric structure is a composite of low-k and high-k dielectric materials, combining the leakage-blocking properties of low-k material with the high-capacitance properties of high-k material to achieve both low leakage and strong gate control simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces off-state leakage current and enhances switching speed by preventing electrical communication between the nanowires and the substrate, while maintaining the gate control over all surfaces of the GAA bodies.
Implementation Method 1
a low dielectric constant (low-k) material between the substrate and the first GAA semiconductor body
Implementation Method 2
the increased capacitance of high-k dielectric materials between nanowires closest to the substrate
Data Source
AI summary
Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.