GAA Semiconductor Structure with Dielectric Source/Drain Segmentation
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Solution Overview
Problem
As integrated circuit (IC) technologies progress towards smaller technology nodes, existing contact features for source/drain in gate-all-around (GAA) transistors impact isolation margins and cost, limiting the effectiveness of existing fabrication technologies for scaling down GAA transistors and circuit cells.
Innovation Solution
The approach involves forming dielectric structures to cut merged source/drain features and channels in a large active area into two portions for each transistor, reducing the impact of process variations and errors, and replacing dummy gate structures with gate structures that wrap around nanostructures, thereby improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing contact features for source/drain in GAA transistors are used, then fabrication process is simpler, but isolation margin deteriorates and cost increases
Solution Approach 1:
The patent divides the merged source/drain features into separate source and drain regions by forming isolation structures between them. This segmentation allows independent optimization of source and drain contacts, improving isolation margin while maintaining fabrication efficiency through standardized processes.
2Area of moving object
If GAA transistors are scaled down to smaller technology nodes, then chip footprint is reduced, but existing contact features impact isolation margin and cost
Solution Approach 1:
The patent transitions from planar contact features to vertically-oriented contact structures that wrap around the nanosheet channels. This dimensional change allows better isolation at scaled dimensions while maintaining electrical connectivity, effectively resolving the isolation margin issue at smaller technology nodes.
3Ease of manufacture
If dummy gate structures are used, then fabrication is easier, but transistor performance is limited
Solution Approach 1:
The patent forms gate structures that wrap around the nanosheet channels before finalizing the source/drain regions. This preliminary gate formation enables better control over the transistor characteristics during subsequent processing steps, improving performance while maintaining fabrication simplicity through self-aligned processes.
Data Source
AI summary
A method for manufacturing a semiconductor structure includes defining active areas extending in an X-direction, arranged in a Y-direction, and on a substrate. Each of the active areas has nanostructures. The method further includes forming dummy gate structures across the active areas in the Y-direction, forming merged source/drain features in the active areas and on opposite sides of the dummy gate structures in the X-direction, forming dielectric structures in the active areas to cut each of the merged source/drain features into a first source/drain feature and a second source/drain feature, and to cut each of the dummy gate structures into segments, and replacing the segments of the dummy gate structures with gate structures wrapping around the nanostructures in the active areas. The dielectric structures are in contact with sidewalls of the first source/drain features, the second source/drain features, and the gate structures.