Side Vertical Contacts in GAA Standard Cells for Lower Parasitic Resistance
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Solution Overview
Problem
Conventional semiconductor devices face challenges with increasing silicide interface resistance due to shrinking cell heights and gate pitches, leading to higher parasitic resistance as the nanosheet count grows, which is exacerbated by limited contact areas and vertical current flow through resistive epi.
Innovation Solution
Implementing side vertical contacts (SVCs) that increase the silicide contact area without significantly increasing cell height, using highly selective CVD TiSi processes to grow silicide around exposed epi areas, and incorporating frontside and backside contacts to enhance electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional contact structures are used, then device scaling is achieved, but parasitic resistance increases due to limited contact area
Solution Approach 1:
The patent introduces side vertical contacts that extend laterally from the frontside contact into the source/drain region, transforming the contact geometry from a single-plane interface to a three-dimensional structure. This dimensional change increases the effective contact area without increasing the vertical cell height, thereby reducing parasitic resistance while maintaining device scaling.
Solution Approach 2:
The side vertical contact is nested within the source/drain region, with the contact structure embedded laterally alongside the channel. This nesting approach allows the contact to occupy space within the existing device footprint rather than requiring additional lateral or vertical space, achieving increased contact area without compromising device density.
2Reliability
If contact area is increased to reduce resistance, then parasitic resistance decreases, but cell height increases
Solution Approach 1:
Instead of increasing contact area vertically by extending cell height, the patent utilizes lateral extension of the contact into the source/drain region. This redirects the area increase from the vertical dimension to the lateral dimension, maintaining constant cell height while achieving the desired contact area expansion for reduced parasitic resistance.
Solution Approach 2:
The side vertical contact is positioned locally within the source/drain region adjacent to the channel, concentrating the contact area increase specifically where it is most effective for current flow. This localized approach avoids unnecessary increases in overall cell height while achieving the resistance reduction goal at the critical contact interface.
3Productivity
If nanosheet count is increased, then device performance improves, but silicide interface resistance increases
Solution Approach 1:
The side vertical contact creates an additional lateral interface between the silicide contact material and the epitaxial source/drain region. This extra interface dimension provides additional parallel conduction paths for current flow, compensating for the increased resistance that occurs when multiple nanosheets are stacked vertically.
Solution Approach 2:
The contact structure is segmented into a frontside contact portion and a side vertical contact portion, creating multiple separate contact interfaces with the source/drain region. This segmentation distributes the current flow across multiple interfaces rather than relying on a single contact area, reducing the overall parasitic resistance even as nanosheet count increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces parasitic resistance by maximizing contact area, allowing for efficient power and signal distribution in semiconductor devices, particularly in gate-all-around (GAA) and forksheet (FS) architectures.
Implementation Method 1
a side vertical contact (SVC) in contact with a side surface of the S/D
Implementation Method 2
using highly selective CVD TiSi processes to grow silicide around exposed epi areas
Data Source
AI summary
Disclosed are semiconductor cells with side vertical contacts (SVCs) in contact with epitaxial source/drains (S/Ds). The SVCs increase the silicide contact area in between middle-of-line (MOL) contacts and the S/Ds. This can significantly reduce contact resistance at the silicide interface, which in turn can reduce the overall parasitic resistance of the cell.