Gate-All-Around Spacer Oxidation for Lower Parasitic Capacitance

The patent segments the channel structure into alternating semiconductor layers (e.g., Si and SiGe) with different etch selectivity and oxidation rates. This segmentation enables selective removal and modification of specific layers, allowing complex 3D gate structures to be formed through controlled etching and oxidation processes rather than requiring entirely new fabrication approaches.

The patent applies local quality by creating regions with different material properties within the channel structure. The alternating layers have different etch selectivity and oxidation rates, enabling localized modification during processing. This allows the gate structure to wrap around the channel from all sides (gate-all-around) with precise control over which regions are etched or oxidized, facilitating complex 3D structures at scaled dimensions.

The patent transitions from conventional planar gate structures to gate-all-around structures where the gate electrode wraps around the channel in three dimensions. This dimensional change reduces parasitic capacitance by minimizing the overlap area between the gate and source/drain regions while maintaining effective gate control. The alternating layer structure enables this 3D configuration through selective etching and oxidation processes.

The patent utilizes parameter changes in material properties, specifically the different oxidation rates of alternating semiconductor layers. By controlling oxidation conditions, the patent selectively oxidizes certain layers to form insulating regions that reduce parasitic capacitance while preserving conductive channel regions. This parameter-based differentiation enables performance improvement through standard fabrication processes.