GAA Transistor Backside Via Epitaxial Regrowth
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Solution Overview
Problem
In the semiconductor industry, particularly in nanometer technology process nodes, three-dimensional designs like Fin FETs and GAA FETs face challenges due to incomplete gate control over the channel region, leading to issues such as channel width variations and increased leakage currents in Fin FETs, and short-channel effects in GAA FETs.
Innovation Solution
The development of gate-all-around (GAA) transistors with backside vias and epitaxial regrowth layers, which provide enhanced electrostatic control and reduce contact resistance by forming a high-quality epitaxial regrowth layer on the backside of source epitaxial structures, allowing for better routing space and improved transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Fin FET gate structure surrounds the fin on three surfaces, then the transistor has three gates controlling the current through the fin, but the fourth side (bottom part of the channel) is far away from the gate electrode and thus is not under close gate control
Solution Approach 1:
The patent introduces a backside gate electrode positioned at the bottom surface of the channel region, inverting the conventional gate placement approach. This backside gate provides direct control over the previously uncontrollable fourth side of the channel, achieving full gate-all-around control while maintaining structural feasibility through the inversion of gate positioning strategy
2Reliability
If GAA FET uses gate electrode surrounding all side surfaces of the channel region, then fuller depletion in the channel region is achieved and short-channel effects are reduced, but fabrication complexity increases
Solution Approach 1:
The gate structure is segmented into multiple independent components: front gate electrodes positioned at the top surfaces of adjacent channel regions and a backside gate electrode positioned at the bottom surface. This segmentation allows each gate component to be fabricated and controlled independently, simplifying the overall manufacturing process while achieving the desired gate-all-around electrostatic control
Solution Approach 2:
A gate dielectric layer is introduced as an intermediary between the gate electrodes (front and backside) and the channel region. This dielectric layer facilitates the electrical isolation and control mechanism, enabling the gate electrodes to exert electrostatic control over the channel while managing the complexity of having gates on all sides
3Productivity
If semiconductor industry progresses into nanometer technology process nodes for higher device density, then device density and performance improve, but fabrication and design challenges increase
Solution Approach 1:
The patent transitions from conventional planar or partial 3D gate structures to a true three-dimensional gate-all-around configuration by adding the backside gate electrode dimension. This dimensional expansion enables continued scaling to nanometer nodes by providing enhanced electrostatic control that counteracts the increased complexity and short-channel effects inherent in smaller process nodes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves electrostatic control over the channel region, reduces leakage currents, and mitigates short-channel effects, resulting in more efficient and densely packed integrated circuit structures with reduced contact resistance.
Implementation Method 1
forming a high-quality epitaxial regrowth layer on the backside of source epitaxial structures
Data Source
AI summary
An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.