GAA Transistor Threshold Tuning with Conformal Dipole Layers
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Solution Overview
Problem
The challenge of achieving multiple threshold voltages in field effect transistors (FETs) on the same substrate is constrained by the thickness limitations of work function metal layers, particularly in gate-all-around (GAA) FETs, which become increasingly difficult with scaling down, and depositing precise thicknesses becomes challenging.
Innovation Solution
Incorporating a dipole layer into the gate dielectric layer using a cyclic deposition etch (CDE) process in an atomic layer deposition (ALD) chamber to form a uniformly thick and conformal dipole layer, combined with work-function tuning layers, to adjust the threshold voltage of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If work function metal layer thickness is varied to achieve multiple threshold voltages, then threshold voltage tuning is possible, but manufacturing precision deteriorates due to thickness limitations and scaling challenges
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate dielectric layer by incorporating dipole layers with specific dipole moments. This allows threshold voltage tuning through material composition changes rather than thickness variations, achieving multiple threshold voltages while maintaining precise manufacturing control.
Solution Approach 2:
The dipole layer acts as an intermediary between the work function metal layer and the channel, providing threshold voltage tuning functionality. This intermediary layer enables precise threshold voltage control without requiring precise control of the work function metal layer thickness, thereby resolving the manufacturing precision challenge.
2Length of moving object
If work function metal layer thickness is reduced for scaling, then device size decreases, but threshold voltage tuning precision deteriorates
Solution Approach 1:
The patent transitions from controlling threshold voltage through geometric parameter (thickness) to controlling it through material parameter (dipole moment and concentration). This allows precise threshold voltage tuning even as device dimensions scale down, maintaining manufacturing precision while reducing device size.
Solution Approach 2:
The patent moves the threshold voltage control mechanism from the vertical dimension (metal layer thickness) to the compositional dimension (dipole layer composition and dipole moment). This dimensional shift enables precise threshold voltage control independent of device scaling, resolving the contradiction between size reduction and precision maintenance.
3Adaptability or versatility
If multiple threshold voltages are achieved through work function metal layer thickness variation, then transistor functionality increases, but process complexity increases
Solution Approach 1:
The patent combines the threshold voltage tuning functionality with the gate dielectric layer formation process. By incorporating dipole layers into the gate dielectric stack, the patent achieves multiple threshold voltages through a unified structure rather than requiring separate processing steps for different metal layer thicknesses, thereby reducing process complexity.
Solution Approach 2:
The gate dielectric layer is designed to serve multiple functions: electrical insulation and threshold voltage tuning. The dipole layer within the gate dielectric provides universal threshold voltage control that applies to all transistors on the substrate, enabling diverse transistor functionalities without increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise tuning of threshold voltages with minimal variation, enabling the fabrication of transistors with different threshold voltages on the same substrate, enhancing the performance and efficiency of semiconductor devices.
Implementation Method 1
a dipole layer is formed over the gate dielectric layer
Implementation Method 2
A thermal drive-in process is performed to drive the dipole metal elements in the dipole layer into the gate dielectric layer
Data Source
AI summary
A method for tuning a threshold voltage of a transistor is disclosed. A channel layer is formed over a substrate. An interfacial layer is formed over and surrounds the channel layer. A gate dielectric layer is formed over and surrounds the interfacial layer. A dipole layer is formed over and wraps around the gate dielectric layer by performing a cyclic deposition etch process, and the dipole layer includes dipole metal elements and has a substantially uniform thickness. A thermal drive-in process is performed to drive the dipole metal elements in the dipole layer into the gate dielectric layer to form an interfacial dipole surface, and then the dipole layer is removed.