GAA Transistor Layer Layout for Tunable Drive Current
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Solution Overview
Problem
The complexity of semiconductor manufacturing processes increases with the scaling down of semiconductor devices, necessitating improved methods to optimize power consumption and drive current characteristics in transistors.
Innovation Solution
The fabrication of GAA FETs with varying numbers of active nanostructured layers between source/drain regions, controlled by dummy epitaxial layers, to achieve different drive current characteristics, and the use of self-aligned back-side contact structures to reduce current leakage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of nanostructured layers is increased to improve drive current, then the transistor performance is enhanced, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the transistor structure into multiple discrete nanostructured layers (e.g., 1-7 layers) between source and drain regions, allowing independent control of each layer's contribution to drive current. This segmentation enables precise tuning of electrical characteristics while maintaining manufacturability through standardized fabrication processes for each layer type.
Solution Approach 2:
The patent implements different numbers of nanostructured layers in different regions of the same semiconductor device (first transistor region vs. second transistor region), creating local variations in drive current characteristics. This local quality approach allows optimization of specific device regions for high-performance applications while maintaining lower complexity in other regions.
2Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs nested structures where multiple nanostructured layers are stacked vertically within the transistor channel region, creating a three-dimensional architecture that increases processing capability without proportionally increasing planar footprint. This nesting approach enables higher performance while controlling manufacturing complexity through vertical integration rather than lateral expansion.
3Loss of energy
If more active nanostructured layers are used to enhance drive current, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent systematically varies the number of active nanostructured layers (parameter) to optimize the balance between drive current and power consumption. By controlling this key parameter across different device regions, the patent achieves energy efficiency optimization without requiring fundamentally new device architectures, thereby limiting the increase in overall system complexity.
Data Source
AI summary
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second dummy epitaxial layers disposed in first and second base structures, first and second active epitaxial layers disposed on the first and second dummy epitaxial layers, a first active nanostructured layer disposed adjacent to and in contact with the first active epitaxial layer, a second active nanostructured layer disposed adjacent to and in contact with the second active epitaxial layer, a dummy nanostructured layer disposed adjacent to and in contact with the second dummy epitaxial layer, a first gate structure surrounding the first active nanostructured layer, and a second gate structure surrounding the second active nanostructured layer and the dummy nanostructured layer.