GAA Transistor Structure With Tapered Trenches for Void-Free Epitaxy
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Solution Overview
Problem
Conventional gate-all-around (GAA) transistors face challenges such as poor epitaxial growth in the source/drain region, small formation margin for gate dielectric and electrode in narrow channel-channel spaces, and increased capacitance between adjacent conductive regions, which are exacerbated as device size is scaled down.
Innovation Solution
A bottom-up epitaxial growth process is employed to form source/drain regions without voids, with a large formation margin for gate dielectric and electrode, and reduced capacitance between source/drain and active gate structures through a method involving selective etching and conformal epitaxial growth in tapered trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GAA device fabrication methods are used, then gate control is improved through gate-all-around structure, but epitaxial growth quality deteriorates in the source/drain region
Solution Approach 1:
The method performs preliminary actions by forming tapered trenches with specific geometry before epitaxial growth, and by preparing the source/drain regions with controlled doping profiles in advance. The tapered trench structure is created prior to the epitaxial growth step, establishing favorable conditions for high-quality growth by providing gradual sidewall angles that prevent void formation and enable uniform material deposition throughout the trench depth.
2Productivity
If device size is scaled down, then production efficiency is improved and costs are reduced, but formation margin for gate dielectric and electrode deteriorates in narrow channel spaces
Solution Approach 1:
The invention transitions from two-dimensional planar scaling to three-dimensional trench structures with controlled sidewall angles. By creating tapered trenches that extend vertically into the substrate, the method adds a depth dimension that provides sufficient formation margin for gate dielectric and electrode layers even when lateral dimensions are reduced. The tapered geometry ensures adequate space throughout the trench depth for complete layer formation without compromising manufacturing precision.
3Reliability
If device size is scaled down, then gate control is improved, but capacitance between adjacent conductive regions increases
Solution Approach 1:
The method applies local quality by creating non-uniform doping profiles within the source/drain regions, with different doping concentrations at different locations within the trench structure. The tapered trench geometry also creates local variations in the electric field distribution, with the wider upper portion providing greater spacing between adjacent conductive regions and thus reduced capacitance, while the narrower lower portion maintains effective gate control over the channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures void-free source/drain regions, ample formation margin for gate dielectric and electrode, and decreased capacitance, enhancing the performance and manufacturability of GAA devices.
Implementation Method 1
A bottom-up epitaxial growth process is employed to form source/drain regions without voids
Data Source
AI summary
The present disclosure provides an integrated circuit (IC) device, including: a semiconductor substrate having a top surface; a first source/drain feature and a second source/drain feature disposed on the semiconductor substrate; and a plurality of semiconductor layers including a first semiconductor layer and a second semiconductor layer. Each of the first semiconductor layer and the second semiconductor layer extends longitudinally in a first direction and connects the first source/drain feature and the second source/drain feature. The first semiconductor layer is stacked over the second semiconductor layer in a second direction perpendicular to the first direction. A length of the first semiconductor layer along the first direction is less than a length of the second semiconductor layer along the first direction. The IC device further includes a gate structure engaging center portions of the first semiconductor layer and the second semiconductor layer.