GAAFET Air-Gap Inner Spacers for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional gate-all-around field effect transistor (GAAFET) processing techniques struggle with proper formation and functioning of inner spacers as device size scaling continues, particularly due to challenges in achieving the required minimum gap for parasitic gate to source/drain capacitance reduction.
Innovation Solution
The implementation of air-gap inner spacers between the gate and source/drain regions, formed through a method that includes creating inner spacer cavities, lining them with a dielectric liner, and sealing with interlayer dielectric material to minimize parasitic capacitance while allowing for device size scaling without violating gap requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional GAAFET processing techniques are used, then device size scaling is limited, but manufacturing complexity increases and minimum gap requirements cannot be met
Solution Approach 1:
The inner spacer is divided into two distinct parts: a first inner spacer portion formed adjacent to the gate structure, and a second inner spacer portion formed adjacent to the source/drain region. This segmentation allows each portion to be optimized independently for its specific function, enabling device scaling while maintaining manufacturability through standardized formation processes for each segment.
Solution Approach 2:
An intermediate structure (the first inner spacer portion) is introduced between the gate structure and the source/drain region, with the second inner spacer portion bridging the gap. This intermediary approach allows the structure to meet minimum gap requirements while maintaining electrical isolation, resolving the contradiction between scaling down device dimensions and maintaining manufacturable gap distances.
2Object-affected harmful factors
If inner spacers are formed to reduce parasitic capacitance, then electrical isolation improves, but manufacturing precision requirements increase
Solution Approach 1:
By segmenting the inner spacer into two portions with distinct formation methods, the patent reduces the precision requirement for each individual portion compared to forming a single continuous inner spacer. The first portion can be formed with standard precision adjacent to the gate, while the second portion adjacent to the source/drain region can be formed independently with appropriate precision, making the overall structure manufacturable while still achieving the capacitance reduction benefit.
Solution Approach 2:
Different regions of the inner spacer structure are given different properties and formation methods: the first portion near the gate uses one formation approach optimized for gate adjacency, while the second portion near the source/drain uses another approach optimized for source/drain adjacency. This local differentiation allows each region to meet its specific requirements without imposing excessive precision demands on the entire structure.
3Productivity
If device size is scaled down, then device density increases, but minimum gap requirements cannot be satisfied
Solution Approach 1:
The inner spacer is segmented into two portions that can be optimized for different spacing requirements. The first portion can be positioned to maintain adequate distance from the gate, while the second portion can extend toward the source/drain region, allowing the overall structure to fit within scaled-down device dimensions while still satisfying minimum gap requirements for electrical isolation.
Solution Approach 2:
The patent utilizes vertical dimensionality by forming the inner spacer portions at different heights or positions relative to the gate and source/drain regions. This dimensional approach allows the structure to maintain adequate horizontal spacing (satisfying minimum gap requirements) while optimizing vertical space utilization to achieve high device density in scaled technologies.
Data Source
AI summary
Disclosed are structures including a gate-all-around field effect transistor (GAAFET) with air-gap inner spacers. The GAAFET includes a stack of nanoshapes that extend laterally between source/drain regions, a gate that wraps around a center portion of each nanoshape, and a gate sidewall spacer on external sidewalls of the gate. The GAAFET also includes air-gap inner spacers between the gate and the source/drain regions. Each air-gap inner spacer includes: two vertical sections within the gate sidewall spacer on opposing sides of the stack and adjacent to a source/drain region; and horizontal sections below the nanoshapes and extending laterally between the vertical sections. Also discloses are methods of forming the structures and the method include forming preliminary inner spacers in inner spacer cavities prior to source/drain region formation. After source/drain regions are formed, the preliminary inner spacers are removed and the cavities are sealed off, thereby forming the air-gap inner spacers.