GaN HEMT with Segmented Barrier for Normally-Off Operation
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Solution Overview
Problem
The existing group-III nitride HFETs with InxAlyGa1-x-yN electronic barrier layers face challenges in providing a normally-off property and high sheet resistance due to large spontaneous polarization and crystalline property deterioration during p-type layer growth, leading to increased sheet resistance and poor temperature tolerance.
Innovation Solution
A field effect transistor configuration is developed with specific nitride semiconductor layers and a recess structure that includes a p-type nitride semiconductor layer at the recess, allowing for precise threshold control and low current leakage, utilizing a substrate with multiple nitride semiconductor layers and a gate electrode configuration that penetrates through multiple layers to reach the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type nitride semiconductor layer is formed at a recess in the InxAlyGa1-x-yN electronic barrier layer, then the transistor should have normally-off property, but the large spontaneous polarization in InxAlyGa1-x-yN reduces the effectiveness of the recess in reducing piezoelectric polarization charge
Solution Approach 1:
The electronic barrier layer is segmented into two parts: an upper InxAlyGa1-x-yN layer providing high spontaneous polarization for carrier density, and a lower AlGaN layer providing piezoelectric polarization for normally-off property. This segmentation allows each layer to fulfill its specific function without interference.
Solution Approach 2:
The patent uses a composite structure combining InxAlyGa1-x-yN and AlGaN materials in the electronic barrier layer. The InxAlyGa1-x-yN layer contributes high spontaneous polarization while the AlGaN layer contributes piezoelectric polarization, creating a synergistic effect that achieves both high carrier density and normally-off property.
2Manufacturing precision
If the crystalline growth temperature for the p-type layer is increased to approximately 1100° C., then the p-type layer can grow properly, but the InxAlyGa1-x-yN electronic barrier layer deteriorates and sheet resistance increases due to nitride escape
Solution Approach 1:
The InxAlyGa1-x-yN layer is formed first as a template layer at lower temperature (approximately 900° C.), and then the p-type AlGaN layer is grown at higher temperature (approximately 1100° C.). This preliminary action protects the sensitive InxAlyGa1-x-yN layer from high-temperature damage while still allowing proper p-type layer formation.
Solution Approach 2:
The patent changes the growth temperature parameter between forming different layers: approximately 900° C. for the InxAlyGa1-x-yN electronic barrier layer and approximately 1100° C. for the p-type nitride semiconductor layer. This parameter change allows optimal growth conditions for each layer type.
3Object-generated harmful factors
If the recess depth is increased to reduce piezoelectric polarization charge, then more charge can be reduced, but the manufacturing complexity and difficulty of controlling threshold voltage increase
Solution Approach 1:
The patent applies local quality by creating a recess only in specific regions where gate electrodes are positioned, rather than uniformly across the entire device. The recess depth and presence are locally optimized to reduce piezoelectric charge where needed while maintaining device performance elsewhere.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration enables a field effect transistor with a normally-off property and high current operation while maintaining low current leakage and stable threshold control, independent of the depth of the recess and impurity implantation profile.
Implementation Method 1
The carrier density can be increased by increasing spontaneous polarization of the electronic barrier layer
Implementation Method 2
the two dimensional electron gas (2DEG) generated at a heterojunction interface between, for example, an aluminum gallium nitride (AlxGa1-xN (0≤x≤1)) electronic barrier layer and a gallium nitride (GaN) channel layer
Data Source
AI summary
A field effect transistor having a reduced sheet resistance is provided. A channel layer, a first spacer layer, a second spacer layer, a first electronic barrier layer, and a second electronic barrier layer are sequentially grown on the main surface of a substrate. A gate recess is created, and then an ion implanted section is formed. A third electronic barrier layer and a p-type layer are formed by a metalorganic chemical vapor deposition (MOCVD) method. The p-type layer except a portion at the gate recess is removed. B ions are implanted in the regrown third electronic barrier layer to reform the ion implanted section. A source electrode and a drain electrode are formed on the third electronic barrier layer. Then a gate electrode is formed on the p-type layer.