GaN Power Transistor with Recessed PN Junction Gate

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Solution Overview

Problem

Conventional power devices using AlGaN/GaN HEMTs face challenges in achieving normally-OFF operation with high current capability due to high threshold voltage and increased gate leak current, which limits their performance in power applications.

Innovation Solution

The semiconductor device incorporates a p-type nitride semiconductor layer with a recessed structure, a carrier supply layer having a greater bandgap, and a 2DEG layer formed between the third and fourth nitride semiconductor layers, allowing for a pn junction sandwiched between the gate electrode and the 2DEG layer, reducing 2DEG concentration and enhancing forward voltage, enabling normally-OFF and high-current operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a conventional AlGaN/GaN HEMT structure is used to achieve high current capability, then the current conduction is improved, but the gate leak current increases and normally-OFF operation becomes difficult

Engineering Contradiction:
Improvecurrent capabilityVSAvoidgate leak current
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The gate structure is segmented into multiple functional layers: a p-type nitride semiconductor layer forming a pn junction with the channel layer, and a separate Schottky barrier gate electrode. This segmentation allows the pn junction to provide normally-OFF characteristics while the Schottky gate maintains high current capability, resolving the contradiction between current capability and gate leak current.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The p-type nitride semiconductor layer acts as an intermediary between the channel layer and the gate electrode. It forms a pn junction that depletes the 2DEG channel at zero gate bias, providing normally-OFF operation, while allowing controlled current flow when biased, thus mediating between the conflicting requirements of high current capability and low gate leak current.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If the gate length is reduced to enable high-speed operation, then the operation speed is improved, but the control over 2DEG concentration becomes more difficult

Engineering Contradiction:
Improveoperation speedVSAvoidcontrol over 2DEG concentration
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The invention changes the fundamental parameter of gate control mechanism from direct electric field modulation in a short gate to pn junction depletion control. The pn junction provides strong depletion of the 2DEG channel through minority carrier injection, enabling effective control even with reduced gate length, thus achieving both high-speed operation and maintainable 2DEG control.

Inventive Principle:
Principle #35Parameter changes

3Speed

If a short gate is used to achieve high-speed operation, then the operation speed is improved, but the forward voltage is reduced

Engineering Contradiction:
Improveoperation speedVSAvoidforward voltage
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The gate structure is segmented into a p-type nitride semiconductor layer that forms a pn junction and a separate Schottky barrier gate electrode. The pn junction provides forward voltage through its diode characteristics, while the Schottky gate maintains the short gate length for high-speed operation, thus resolving the contradiction between forward voltage and operation speed.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves forward voltage, reduces gate leak current, and allows for both normally-OFF and high-current operations, while enabling a short gate length for high-speed performance, thus addressing the limitations of conventional power devices.

Implementation Method 1

a pn junction is formed between the p-type nitride semiconductor layer and the third nitride semiconductor layer

Methodology Applied
Scientific Effectpn junction: Diode

Implementation Method 2

a depletion layer (not shown) across a Schottky barrier, whereby a current in 2DEG layer 7 is controlled

Methodology Applied
Scientific Effectdepletion layer: Electrical Resistance

Implementation Method 3

a high-concentration electron channel (two-dimensional electron gas which is referred to as 2DEG below) is generated in the GaN layer near an interface of the AlGaN/GaN layers due to piezoelectric charges generated from a difference in lattice constant between the AlGaN and the GaN layers, and a difference in bandgap between the AlGaN and the GaN layers

Methodology Applied
Scientific Effect2DEG layer: Conduction (electrical)

Implementation Method 4

Gate electrode 10 makes a Schottky contact with carrier supply layer 6

Methodology Applied
Scientific EffectSchottky contact: Electrical Resistance

Implementation Method 5

a depletion layer (not shown) across a Schottky barrier, whereby a current in 2DEG layer 7 is controlled

Methodology Applied
Scientific EffectSchottky barrier: Electrical Resistance

Data Source

PatentUS9412858B2Group III nitride semiconductor device which can be used as a power transistor
Publication Date: 2016.08.09 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
  • US9412858B2 patent drawing
  • US9412858B2 patent drawing
  • US9412858B2 patent drawing

AI summary

A semiconductor device includes a substrate, a first nitride semiconductor layer formed on the substrate, a p-type nitride semiconductor layer formed on the first nitride semiconductor layer, a recess having a bottom portion which reaches the first nitride semiconductor layer through a part of the p-type nitride semiconductor layer, a third nitride semiconductor layer formed to cover the bottom portion of the recess, a side portion of the recess, and a part of an upper surface of the p-type nitride semiconductor layer. The semiconductor device further includes a fourth nitride semiconductor layer formed on the third nitride semiconductor layer, a first electrode formed on another side of the substrate, a gate electrode formed on the upper surface of the p-type nitride semiconductor layer, and a second electrode that is in contact with the third nitride semiconductor layer or the fourth nitride semiconductor layer. The third nitride semiconductor layer has a bandgap different from a bandgap of the fourth nitride semiconductor layer.