Gallium Oxide Substrate Chamfer Geometry for Edge Damage Suppression

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Solution Overview

Problem

Existing semiconductor substrates made of different materials, such as glass and gallium oxide-based semiconductors, require specific chamfered shapes to effectively prevent damage during manufacturing and handling, which are not universally applicable.

Innovation Solution

A gallium oxide-based semiconductor substrate with a chamfered portion at its outer periphery, featuring inclined surfaces and an end face, is designed to suppress damage during polishing, conveyance, and handling, with the chamfered portion's dimensions optimized to prevent cleavage and scratches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a chamfered portion is provided at the outer periphery of a semiconductor substrate, then damage during handling and manufacturing is suppressed, but the substrate occupies more space and has increased structural complexity

Engineering Contradiction:
Improvedamage suppressionVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention applies chamfering only to the outer periphery portion of the semiconductor substrate, specifically at locations where damage is most likely to occur during handling and manufacturing. This localized application of the chamfered structure provides protective function exactly where needed, rather than modifying the entire substrate structure, thus balancing damage suppression with minimal structural complexity increase.

Inventive Principle:
Principle #3Local quality

2Reliability

If the chamfered portion dimensions are increased to better prevent damage, then damage suppression improves, but the substrate area is reduced and manufacturing precision requirements increase

Engineering Contradiction:
Improvedamage suppressionVSAvoidchamfered portion dimensions
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The invention specifies optimal parameter ranges for the chamfered portion, including the width being 5-50 μm and the inclined surface angle being 45 degrees. These parameter values are carefully selected to provide sufficient damage protection while maintaining manufacturability with conventional precision capabilities. The parameters are optimized to balance protective function with manufacturing feasibility.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the chamfered portion width is increased to prevent cleavage, then damage suppression improves, but the substrate area is reduced

Engineering Contradiction:
Improvecleavage preventionVSAvoidsubstrate area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The chamfered portion is applied locally at the outer periphery of the substrate where cleavage damage is most likely to occur during handling. By concentrating the protective structure only at the vulnerable edges rather than across the entire substrate, the invention prevents cleavage while minimizing the reduction of usable substrate area.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention applies a relatively narrow chamfered width (5-50 μm) which is sufficient to prevent cleavage damage at the edges without excessively reducing the overall substrate area. This partial action provides the necessary protection while maintaining adequate substrate area for device fabrication.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3888846B1Semiconductor substrate and method for manufacturing the same
Publication Date: 2025.01.29 NOVEL CRYSTAL TECH INC
  • EP3888846B1 patent drawingFigure 1
  • EP3888846B1 patent drawingFigure 2A~2B
  • EP3888846B1 patent drawingFigure 3

AI summary

A semiconductor substrate includes a gallium oxide-based semiconductor single crystal and a chamfered portion at an outer periphery portion. The chamfered portion includes a first inclined surface located on the outer side of a first principal surface of the semiconductor substrate and being linear at an edge in a vertical cross section of the semiconductor substrate, a second inclined surface located on the outer side of a second principal surface on the opposite side to the first principal surface and being linear at an edge in the vertical cross section, and an end face located between the first inclined surface and the second inclined surface at a leading end of the chamfered portion. A width of the end face in a thickness direction of the semiconductor substrate is within the range of not less than 50% and not more than 97% of a thickness of the semiconductor substrate.