Encapsulated Semiconductor Chip with Galvanic Contact Pads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The cost-intensive process of packaging semiconductor chips, particularly in creating efficient electrical access and thermal management, limits the manufacturing efficiency and performance of semiconductor devices.
Innovation Solution
A method involving a carrier with a dielectric layer and a galvanically grown metal layer to form external contact pads, allowing semiconductor chips to be encapsulated with a redistribution layer that extends beyond the chip's outline, enabling increased contact area and reduced conductor line dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional packaging methods are used to provide electrical access to semiconductor chips, then the chips are protected from environmental stresses, but the package pad size and pitch are constrained, increasing manufacturing cost
Solution Approach 1:
The patent extends the conductor lines and contact pads into the third dimension by forming them on the underside of the encapsulation body, below the semiconductor chip. This dimensional change allows the external contact pads to be positioned outside the chip's footprint, increasing the available area for electrical connections without increasing the chip package size, thereby reducing manufacturing constraints and costs while maintaining protection
2Reliability
If the contact area is increased to improve electrical accessibility, then the electrical access performance improves, but the package pad size constraints are worsened
Solution Approach 1:
The patent positions the external contact pads on the underside of the encapsulation body, utilizing the vertical dimension below the chip to increase the contact area. This allows multiple contact pads to be arranged in a larger area without increasing the horizontal footprint of the package, thus improving electrical accessibility while maintaining compact package dimensions
Solution Approach 2:
The patent separates the external contact pads from the chip's active area by positioning them on the underside of the encapsulation body. This segmentation allows the contact pads to be independently positioned and sized to optimize electrical connections without being constrained by the chip's layout requirements, improving electrical accessibility without increasing the overall package pad size
3Productivity
If the conductor line dimensions are reduced to increase density, then the pitch between contacts is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
By positioning the conductor lines and contact pads on the underside of the encapsulation body, the patent creates additional space for routing and positioning. This allows for reduced pitch between contacts without requiring extremely precise manufacturing of the conductor lines themselves, as the extra dimensional space provides tolerance for alignment variations during manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the constraints on package pad size and pitch, enhancing the electrical accessibility and thermal management of semiconductor chips while decreasing manufacturing costs and improving performance.
Implementation Method 1
a galvanically grown metal layer to form external contact pads
Data Source
AI summary
A method includes providing a carrier; applying a dielectric layer to the carrier; applying a metal layer to the dielectric layer; placing a first semiconductor chip on the metal layer with contact pads of the first semiconductor chip facing the metal layer; covering the first semiconductor chip with an encapsulation material; and removing the carrier.