Gamma Voltage Resistor String Layout for LCD Uniformity
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Solution Overview
Problem
Existing resistor strings in liquid crystal display apparatuses face challenges in achieving high-accuracy voltage division due to contact resistances, leading to relative errors in gradation voltages and display unevenness, which complicates the generation of desired gamma curves and reduces product yield.
Innovation Solution
A multilevel voltage generating circuit with a specific layout pattern where output nodes for maximum and minimum gradation voltages are positioned outside the current path of the static current, utilizing a single resistance element and dummy resistors to minimize the impact of contact resistances, ensuring uniform voltage drops across all gradation voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single resistance element with contacts arranged in the same interval is used, then the device complexity is reduced, but the manufacturing precision of gradation voltages deteriorates due to contact resistance variations
Solution Approach 1:
The patent segments the resistance element into multiple sections with different contact arrangements. Specifically, the first resistance element has contacts arranged at different intervals, with the second interval being longer than the first interval. This segmentation allows different sections to have different contact resistance characteristics, thereby compensating for variations and improving gradation voltage accuracy while maintaining relatively simple device structure.
2Ease of manufacture
If contacts are arranged in the same interval to simplify the layout, then the ease of manufacture is improved, but the reliability of voltage division deteriorates due to accumulated contact resistance errors
Solution Approach 1:
The patent introduces asymmetry in the contact arrangement by setting different intervals between contacts. The second interval between the second and third contacts is deliberately made longer than the first interval between the first and second contacts. This asymmetric design breaks the uniformity that causes accumulated contact resistance errors, thereby improving voltage division reliability while maintaining manufacturing simplicity.
3Manufacturing precision
If division electrodes are defined as low-resistance elements to avoid contact resistance variation, then the manufacturing precision of individual contacts is improved, but the relative errors among division resistors increase due to non-uniform voltage drops
Solution Approach 1:
The patent changes the physical parameter of contact interval to compensate for contact resistance effects. By making the second interval longer than the first interval, the patent creates a parameter variation that counteracts the non-uniform voltage drops caused by contact resistances. This allows the use of low-resistance division electrodes while maintaining division resistor accuracy through the optimized interval configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces relative errors in gradation voltages, improves display uniformity, and enhances the yield of the multilevel voltage generating circuit and liquid crystal display apparatus by uniformly distributing the effects of contact resistances across all gradation voltages.
Implementation Method 1
a single resistance element is provided with contacts and electrodes both arranged in a same interval, each of which outputs a divided voltage
Data Source
AI summary
A multilevel voltage generating circuit includes first and second input nodes provided on a first resistance element and supplied with first and second reference voltages. A current substantially flows in a first specific area for a line between the first and second input nodes based on a difference between the first and second reference voltages. A first group of output nodes are provided for the first resistance element to output a portion of a plurality of level voltages. A first one of the first group of output nodes for one of the plurality of level voltages which is closest to the first reference voltage is provided outside the first specific area. The first output node, the first input node, and the second input node, are arranged on a line on the first resistance element in this order.