GaN Power Amplifier ESD Protection on a Separate Substrate
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Solution Overview
Problem
Gallium nitride (GaN) field effect transistors (FETs) are vulnerable to electrostatic discharge (ESD) events due to the high cost of GaN wafers, making it economically prohibitive to integrate ESD protection circuits directly on the GaN FET die, thus exposing the sensitive gate structure to potential damage during manufacturing and deployment.
Innovation Solution
Implementing an ESD protection circuit on a separate substrate, such as a driver stage die or an integrated passive device (IPD), which includes a GaN FET and an ESD protection circuit configured to clamp high positive ESD voltages and short ESD energy away from the GaN FET without using valuable GaN die area, while maintaining the negative gate bias voltage required for the GaN FET operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection circuit is integrated on GaN FET die, then ESD protection is provided, but wafer cost increases significantly
Solution Approach 1:
The patent divides the ESD protection function from the GaN FET die by implementing it on a separate driver stage die. This segmentation allows the expensive GaN die to maintain its high performance characteristics while the ESD protection circuitry resides on a less expensive substrate, resolving the cost contradiction.
Solution Approach 2:
The driver stage die acts as an intermediary between the ESD-prone environment and the sensitive GaN FET gate. It includes ESD protection circuits that clamp high positive ESD voltages and short ESD energy away from the GaN FET, while maintaining the negative gate bias voltage required for GaN FET operation.
2Reliability
If ESD protection circuit is integrated on GaN FET die, then ESD protection is provided, but GaN die area is consumed
Solution Approach 1:
The ESD protection circuit is extracted from the GaN FET die and implemented on a separate driver stage die. This extraction preserves the valuable GaN die area for the power transistor itself while providing the necessary ESD protection functionality through the driver stage die that includes ESD protection circuits.
3Reliability
If ESD protection circuit is added, then ESD protection is provided, but device complexity increases
Solution Approach 1:
The ESD protection circuits are merged with the driver stage die that already exists in the amplifier architecture. This combining approach provides ESD protection without adding completely separate circuitry, as the driver stage serves dual purposes: signal driving and ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively protects the GaN FET gate structure from ESD events without increasing the GaN die area usage, thereby reducing costs and ensuring the reliability of GaN FETs in high-power amplifier circuits.
Implementation Method 1
the ESD protection circuit configured to clamp high positive ESD voltages and short ESD energy away from the GaN FET
Data Source
AI summary
An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a first RF signal input terminal, a first RF signal output terminal, and a transistor. The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.