GaN Cascode Transistor With Dopant-Blocking Layer
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Solution Overview
Problem
Existing nitride semiconductor devices, such as GaN-HEMTs, face challenges in achieving a normally-off mode with low on-resistance and high withstand voltage due to issues like etching damage, p-type dopant diffusion, and reduced electron mobility, making it difficult to maintain steady operation.
Innovation Solution
A semiconductor device configuration featuring a cascode connection between a normally-on GaN-HEMT and a normally-off GaN-HEMT, with a p-type-dopant-diffusion-blocking layer to prevent p-type dopant diffusion and enhance 2DEG generation, allowing for independent control of the normally-on and normally-off transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If part of the electron supply layer is etched to enable normally-off mode operation, then the device can operate in normally-off mode, but etching damage increases on-resistance and leak current
Solution Approach 1:
The device is divided into two separate transistors: a normally-on GaN-HEMT and a normally-off GaN-HEMT. Each transistor is independently optimized for its specific function, allowing the normally-off transistor to use etching without affecting the normally-on transistor's performance. This segmentation resolves the contradiction by isolating the harmful effects of etching to only the normally-off device.
Solution Approach 2:
A p-type-dopant-diffusion-blocking layer is introduced as an intermediary between the two transistors. This layer prevents p-type dopant diffusion from the normally-off transistor's electron transit layer to the normally-on transistor's electron supply layer, thereby blocking the harmful effect while maintaining the benefits of normally-off operation.
2Ease of operation
If a p-type GaN layer is formed to counteract 2DEG for normally-off mode, then normally-off operation is enabled, but the thickness of the electron supply layer is reduced making it difficult to achieve low on-resistance and high withstand voltage
Solution Approach 1:
The device separates the normally-on and normally-off functions into two distinct transistors. This allows each transistor to have an optimally thick electron supply layer for its specific operation mode, eliminating the need to reduce the electron supply layer thickness for normally-off operation. The normally-on transistor maintains low on-resistance while the normally-off transistor achieves its switching function.
Solution Approach 2:
The invention changes the operational parameter by using a p-type-dopant-diffusion-blocking layer instead of forming a p-type GaN layer. This allows the electron supply layer thickness to be maintained at optimal levels while still achieving normally-off operation through the blocking layer's prevention of 2DEG formation in the normally-off transistor.
3Ease of operation
If the thickness of the electron supply layer is reduced to enable normally-off mode, then normally-off operation is achieved, but the distance between gate and drain electrodes must be increased resulting in increased on-resistance
Solution Approach 1:
By segmenting the device into two separate transistors, each can be independently optimized. The normally-off transistor can use the required thicker distance between gate and drain for normally-off operation without compromising the normally-on transistor's low on-resistance performance. Each transistor operates in its optimal configuration.
Solution Approach 2:
The invention changes the approach to achieving normally-off operation by introducing a p-type-dopant-diffusion-blocking layer, which allows the electron supply layer thickness and gate-drain distance to be optimized independently for low on-resistance while still maintaining normally-off functionality.
4Ease of operation
If a 2DEG-reducing layer doped with p-type dopant is formed to enable normally-off mode and low source resistance, then normally-off operation is enabled, but p-type dopant diffusion during crystal growth increases on-resistance
Solution Approach 1:
A p-type-dopant-diffusion-blocking layer is positioned between the two transistors to act as an intermediary that blocks p-type dopant diffusion during crystal growth. This prevents the harmful diffusion effect while allowing the 2DEG-reducing layer to function properly in the normally-off transistor, thereby resolving the contradiction between normally-off operation and low on-resistance.
5Ease of operation
If part of the electron transit layer is doped with p-type dopant to enable normally-off mode and high withstand voltage, then normally-off operation is achieved, but p-type dopant diffusion during crystal growth increases on-resistance
Solution Approach 1:
The p-type-dopant-diffusion-blocking layer serves as an intermediary that prevents p-type dopant from diffusing during crystal growth. This allows the electron transit layer to be doped with p-type dopant for normally-off operation and high withstand voltage without the harmful side effect of dopant diffusion increasing on-resistance.
6Ease of operation
If the third technique structure with laminated 2DEG-reducing layer and low-resistance layer is used, then normally-off mode is enabled, but electron mobility is low and channel resistance is high resulting in high on-resistance
Solution Approach 1:
The invention segments the device into two separate transistors, allowing the normally-off transistor to use the laminated structure for normally-off operation while the normally-on transistor maintains high electron mobility and low on-resistance. This isolation prevents the high on-resistance of the laminated structure from affecting the overall device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables operation in a normally-off mode with low on-resistance and high withstand voltage by blocking p-type dopant diffusion and increasing electron mobility, reducing on-resistance and maintaining high performance.
Implementation Method 1
p-type-dopant-diffusion-blocking layer to prevent p-type dopant diffusion
Implementation Method 2
strain is generated in AlGaN owing to difference in a lattice constant between AlGaN and GaN, and the strain causes piezoelectric polarization. This piezoelectric polarization and the spontaneous polarization of the AlGaN cause high-concentration two dimensional electron gas (2DEG) to be generated
Data Source
AI summary
A semiconductor device includes: a first transistor that includes a first gate electrode, a first source electrode, a first drain electrode, and a first nitride semiconductor laminate that includes a first electron transit layer and a first electron supply layer; a second transistor that includes a second gate electrode, a second source electrode, a second drain electrode, and a second nitride semiconductor laminate that includes a second electrode transit layer and a second electron supply layer, the second drain electrode being a common electrode that also serves as the first source electrode, the second electron transit layer having part that underlies the second gate electrode and that contains a p-type dopant; and a p-type-dopant-diffusion-blocking layer.