GaN Semiconductor Device With Crystal Phase Channel Layers
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Solution Overview
Problem
The existing semiconductor devices with N-type and P-type channels face challenges in accurately implanting dopants using ion implantation, which results in complex processes and performance issues due to dopant diffusion during high-temperature processes.
Innovation Solution
The semiconductor device employs deposition processes to form GaN channel layers with different crystal phases, separated by isolation layers and barrier layers, eliminating the need for ion implantation and simplifying the manufacturing process while maintaining consistent layer thicknesses to avoid flatness issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is used to implant dopants into channel layers, then N-type and P-type channels can be formed, but the process becomes complex and dopant diffusion occurs during high-temperature processes affecting device performance
Solution Approach 1:
The patent extracts and removes the dopant implantation step from the manufacturing process. Instead of using ion implantation to create doped regions, the invention forms undoped GaN channel layers with specific crystal phases (wurtzite for N-type, rock-salt for P-type) through deposition processes, thereby eliminating the complex dopant implantation and diffusion control issues
Solution Approach 2:
The patent changes the fundamental parameter approach from chemical doping to physical crystal phase control. By controlling deposition parameters (temperature, pressure, gas flow ratios) to produce different crystal phases of GaN, the invention achieves type control without introducing foreign dopant atoms, thus avoiding diffusion problems
2Manufacturing precision
If ion implantation is used to accurately implant dopants, then N-type and P-type channels can be formed, but additional process steps and higher process difficulty are required
Solution Approach 1:
The patent replaces the mechanical ion implantation system with a deposition-based crystal phase control system. Instead of physically shooting ions into the lattice, the invention uses vapor-phase deposition to grow layers with desired crystal structures, significantly simplifying the manufacturing process while maintaining precision through controlled deposition parameters
3Reliability
If dopants are implanted into channel layers, then N-type and P-type channels can be formed, but dopant diffusion during high-temperature processes influences device performance
Solution Approach 1:
The patent converts the harmful effect of high-temperature processing (which causes dopant diffusion) into a beneficial opportunity. By using crystal phase-stable undoped layers, the invention utilizes high-temperature processing to ensure complete amorphization of the gate dielectric and proper interface formation without worrying about dopant migration, thus improving device reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and stabilizes the device performance by avoiding dopant diffusion and the need for additional planarization steps, enabling the creation of complementary metal oxide semiconductor (CMOS) transistors with consistent structure.
Implementation Method 1
a first GaN channel layer disposed on the substrate and having an N crystal phase and a first barrier layer disposed on the first GaN channel layer. The second stacked structure is disposed on the substrate, and includes a second GaN channel layer disposed on the substrate and having a Ga crystal phase
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first stacked structure, a second stacked structure, an isolation layer and a gate. The first stacked structure is disposed on a substrate, and includes a first GaN channel layer disposed on the substrate and having an N crystal phase and a first barrier layer disposed on the first GaN channel layer. The second stacked structure is disposed on the substrate, and includes a second GaN channel layer disposed on the substrate and having a Ga crystal phase and a second barrier layer disposed on the second GaN channel layer. The isolation layer is disposed between the first stacked structure and the second stacked structure. The gate is disposed on the first stacked structure, the isolation layer and the second stacked structure.