GaN Differential Latch for Common-Mode Immune Level Shifting
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Solution Overview
Problem
Existing latch circuits in half-bridge IC designs, particularly those using GaN technology, face issues with common-mode voltage changes corrupting logic values due to fast positive or negative dv/dt at the SW node, leading to undesired state changes and logic value corruption, and require p-FETs that are not feasible in GaN processes.
Innovation Solution
A differential activated cross-coupled latch circuit is designed, implemented using GaN technology, which prevents latch output changes when both inputs are the same, utilizing n-FETs and inverters to maintain logic levels and rejecting common-mode signals, thus avoiding logic value corruption, and does not require p-FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional latch circuit is used with fast dv/dt at SW node, then the latch can respond quickly to input changes, but common-mode voltage changes will corrupt the logic values stored in the latch
Solution Approach 1:
The latch input stage is segmented into two independent differential paths (one for each input signal) that are processed separately through their own n-FET switches and current mirrors. This segmentation isolates the differential signal paths from common-mode interference, allowing fast response while maintaining logic value integrity through differential signaling that rejects common-mode voltage changes.
Solution Approach 2:
A differential amplifier stage is introduced as an intermediary between the input switches and the latch storage element. This intermediary converts the differential input signals into a form that is immune to common-mode voltage changes, thereby protecting the stored logic values from corruption while maintaining fast response capability.
2Reliability
If p-FETs are used in the latch circuit to protect against common-mode voltage, then common-mode rejection is improved, but the circuit cannot be implemented in GaN processes
Solution Approach 1:
The circuit is designed with homogeneity by using only n-FETs throughout the entire latch circuit, including the protection switches and the differential pair. This homogeneous n-FET implementation achieves common-mode rejection through differential signaling and current mirror symmetry, eliminating the need for p-FETs and enabling full GaN process compatibility.
Solution Approach 2:
The circuit topology is changed from a conventional design that relies on p-FET/n-FET complementary pairs to a fully n-FET differential architecture. This parameter change in device type and circuit configuration maintains common-mode rejection capability through differential signaling while adapting the circuit for GaN process manufacturing that lacks reliable p-FET implementation.
3Reliability
If diode-connected FETs are added to protect gate voltages from common-mode voltage, then gate voltage protection is improved, but the circuit complexity increases
Solution Approach 1:
The n-FET switches in the differential input stage serve multiple functions: they act as signal switches for the differential inputs, provide common-mode rejection through their differential configuration, and simultaneously protect the gate voltages of subsequent stages from common-mode voltage excursions. This multi-functionality eliminates the need for separate diode-connected protection FETs, reducing circuit complexity while maintaining comprehensive protection.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A cross-coupled differential activated latch circuit with circuitry comprising a plurality of n-FETs and inverters (72, 74) that can be implemented completely in GaN. The circuitry prevents the digital latched values on the outputs of the latch (24, 26) from changing unless the digital input values on the inputs (20, 22) are different, thus preventing common-mode voltage on the inputs (20, 22 being high or 20, 22 being low) from corrupting the stored latch values (20, 22).