GaN Power IC Driver Partitioning for Low-Parasitic Gate Control
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Solution Overview
Problem
The integration of full drivers with GaN power devices is challenging due to the absence of npn or pnp transistors and the limited performance of p-channel unipolar transistors, leading to high power consumption and heat coupling issues.
Innovation Solution
A power integrated circuit (Power IC) is proposed, comprising a GaN chip with a heterojunction structure and a silicon companion chip. The GaN chip includes a main power device with a 2DEG and a monolithically integrated low-side driver component, while the silicon companion chip hosts the high-side driver component, enabling efficient charging and discharging of the gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If full drivers are integrated with GaN power devices on the same chip, then device complexity is reduced and parasitics are minimized, but the absence of npn or pnp transistors in GaN technology leads to high power consumption and heat coupling issues
Solution Approach 1:
The driver is segmented into two separate chips: a GaN chip containing the power device and low-side driver components, and a silicon companion chip containing the high-side driver components. This segmentation allows each chip to be optimized for its specific function, enabling the GaN chip to operate at high frequency with low power consumption while the silicon chip handles the high-voltage switching functions.
Solution Approach 2:
A hybrid integration approach is used as an intermediary solution, combining GaN technology on one chip with mature silicon technology on another chip. The chips are coupled through a hybrid interface that minimizes parasitics while allowing each material system to operate in its optimal performance regime.
2Device complexity
If full drivers are integrated with GaN power devices on the same chip, then device complexity is reduced, but heat coupling issues arise due to limited thermal management capabilities
Solution Approach 1:
The driver functionality is segmented across two separate chips with different thermal characteristics. The GaN chip, which operates at lower voltages and generates less heat, is separated from the silicon chip, which is better suited for handling the thermal loads associated with high-voltage switching. This segmentation prevents heat coupling between components while maintaining functional integration.
3Ease of manufacture
If p-channel unipolar transistors are used in GaN drivers, then device fabrication is simplified, but performance is limited leading to high power consumption
Solution Approach 1:
The solution uses an intermediary approach by combining GaN technology for the low-side driver (where simple unipolar transistors suffice) with mature silicon technology for the high-side driver (where enhanced performance is needed). This hybrid integration allows each section to use the most appropriate technology for its specific requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces component count and parasitics, enhances high-frequency operation, and improves the stability and efficiency of the driver circuit by leveraging the high electron mobility of GaN and the mature technology of silicon.
Implementation Method 1
The use of an Aluminium Galium Nitride (AlGaN)/GaN heterostructure also allows the formation of a two-dimensional electron gas (2DEG) at the hetero-interface
Implementation Method 2
the piezopolarization charge present at the AlGaN/GaN heterostructure can result in a high electron density in the 2DEG layer
Implementation Method 3
the wide band gap of the material (Eg=3.39 eV) results in high critical electric field (Ec=3.3 MV/cm)
Data Source
AI summary
A power integrated circuit comprising: a heterojunction structure Gallium Nitride, GaN, chip comprising at least one GaN layer and at least one Aluminium Gallium Nitride, AlGaN, layer wherein the GaN chip comprises at least one main power device comprising a source terminal, a drain terminal, a gate terminal and a two-dimensional electron gas, 2DEG, formed at an interface between the AlGaN and GaN layers and between the source and drain terminals, wherein the gate terminal is configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal, a driver comprising at least one low-side component and at least one high-side component, wherein the low-side component comprises a terminal connected to a low DC voltage rail and at least one other terminal connected to the gate terminal of the main power device; wherein the high-side component comprises at least one terminal connected to a high DC voltage rail and at least one other terminal connected to the gate of the main power device; wherein the at least one low-side component of the driver is configured to discharge an input capacitance of the main power device during a turn-off of the main power device and is monolithically integrated within the GaN chip; and wherein the at least one high-side component of the driver is configured to charge up the input capacitance of the main power device and is formed in a semiconductor region comprising a material other than GaN.