GaN FET Depolarization Layer Threshold Voltage Control

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Solution Overview

Problem

GaN-based E-mode FETs have threshold voltages that are too low to meet commercial product application specifications, limiting their operational capabilities.

Innovation Solution

Incorporating a depolarization layer, such as a metal oxide or II-VI semiconductor layer, between the second semiconductor layer and the p+ III-V semiconductor layer, which raises the conduction band and can have varying aluminum content to enhance the threshold voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a GaN-based E-mode FET is designed with conventional structure, then the device can operate in enhancement mode, but the threshold voltage remains too low to meet commercial specifications

Engineering Contradiction:
Improvethreshold voltageVSAvoidoperation mode control
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

A depolarization layer is introduced as an intermediary layer between the AlGaN second semiconductor layer and the p-type III-V semiconductor layer. This depolarization layer, composed of materials such as InGaN or metal oxides (e.g., ZnO, TiO2, SrTiO3), generates a depolarization field that effectively raises the conduction band edge and increases the threshold voltage, enabling the FET to meet commercial specifications while maintaining E-mode operation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the physical and chemical parameters of the semiconductor structure by introducing the depolarization layer with specific piezoelectric polarization properties. The layer's composition, thickness, and material parameters are optimized to generate the appropriate depolarization field strength, thereby controlling the threshold voltage to achieve normally-off operation

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the conduction band is raised to increase threshold voltage, then the FET can achieve normally-off operation, but the electron mobility and concentration in the 2DEG may be affected

Engineering Contradiction:
Improvethreshold voltage controlVSAvoid2DEG quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The depolarization layer is positioned locally between the AlGaN layer and the p-type layer, creating a localized region of high piezoelectric polarization. This local quality change generates a confined depolarization field that raises the conduction band edge in the critical region near the interface, increasing threshold voltage while preserving the overall quality of the 2DEG in other regions

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Effectively raises the conduction band and enhances the ability to deplete electrons, thereby increasing the threshold voltage and enabling normally-off operation mode in FETs.

Implementation Method 1

uses a p-type heavily-doped III-V semiconductor layer (p+ III-V semiconductor layer) in association with a depolarization layer made of a high piezoelectric polarization material thereunder to effectively raise a conduction band (Ec) to be higher than the Fermi energy level

Methodology Applied
Scientific EffectPiezoelectric polarization: Piezoelectric Effect

Data Source

PatentUS9647102B2Field effect transistor
Publication Date: 2017.05.09 ENNOSTAR CORP
  • US9647102B2 patent drawing
  • US9647102B2 patent drawing
  • US9647102B2 patent drawing

AI summary

A field effect transistor includes a substrate; a first semiconductor layer, disposed over the substrate; a second semiconductor layer, disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas; a p+ III-V semiconductor layer, disposed over the second semiconductor layer; and a depolarization layer, disposed between the second semiconductor layer and the p+ III-V semiconductor layer, wherein the depolarization layer includes a metal oxide layer.