Self-Aligned Gate GaN FET for 5G Low Voltage Operation

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Solution Overview

Problem

Current compound semiconductor transistors, such as bipolar and high-electron-mobility transistors, face challenges in meeting the increased transmission frequency specifications for 5G and 5G+ wireless communication systems due to high operating voltages and gate alignment issues, making them unsuitable for mobile devices.

Innovation Solution

A compound semiconductor field effect transistor (FET) with self-aligned gates is developed, using gallium nitride (GaN) material and alloy layers, featuring L-shaped contacts and gate spacers to reduce source/drain-to-gate space, enabling lower operating voltages and improved frequency support.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional compound semiconductor transistors (GaN, HBTs) are used to support higher transmission frequencies for 5G/5G+, then transmission frequency capability is improved, but operating voltage becomes too high for mobile device applications

Engineering Contradiction:
Improvetransmission frequencyVSAvoidoperating voltage
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent modifies the gate structure parameters by introducing self-aligned gates with optimized gate length and width dimensions. This changes the electrical characteristics of the transistor, enabling it to operate at lower voltages while maintaining high frequency performance suitable for mobile devices

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If conventional transistor gate structures are used, then manufacturing is simpler, but gate alignment precision is insufficient to meet future 5G/5G+ transmission frequency specifications

Engineering Contradiction:
Improvegate alignment precisionVSAvoidgate structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent employs preliminary self-alignment actions during fabrication where the gate structure is pre-positioned relative to other components. This preliminary alignment ensures precise gate positioning without requiring complex post-fabrication alignment procedures, achieving high manufacturing precision while controlling device complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediary alignment structures and processes that mediate between the gate and other transistor components. These intermediaries facilitate precise relative positioning during fabrication, enabling high gate alignment precision without proportionally increasing overall device complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If GaAs pseudomorphic HEMTs are used to reduce operating voltage, then operating voltage is lowered for mobile devices, but power density becomes too low for effective power amplifier implementation

Engineering Contradiction:
Improveoperating voltageVSAvoidpower density
Core Design Contradiction:
Use of energy by moving objectVSPower

Solution Approach 1:

The patent utilizes composite material structures combining different semiconductor layers with optimized thicknesses and compositions. This composite approach enables the transistor to achieve both lower operating voltages suitable for mobile devices and sufficient power density for power amplifier applications by leveraging the complementary properties of different material layers

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS10461164B2Compound semiconductor field effect transistor with self-aligned gate
Publication Date: 2019.10.29 QUALCOMM INC
  • US10461164B2 patent drawing
  • US10461164B2 patent drawing
  • US10461164B2 patent drawing

AI summary

A compound semiconductor field effect transistor (FET) may include gallium nitride (GaN) and alloy material layers. The compound semiconductor FET may also include a pair of L-shaped contacts on the GaN and alloy material layers. The compound semiconductor FET may also include a pair of gate spacers between the L-shaped contacts and on the GaN and alloy material layers, each of the pair of gate spacers contacting one of the L-shaped contacts. The compound semiconductor FET may further include a base gate between the pair of gate spacers and on the GaN and alloy material layers, in which the pair of L-shaped contacts are self-aligned with the base gate.