GaN Transistor Field Plate Heights for Breakdown Voltage
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Solution Overview
Problem
Conventional GaN transistors face challenges in achieving both low leakage current and high electron density in the channel simultaneously due to the critical nature of the insulator/barrier interface, which results in a high electric field at the corner of the barrier offset layer, reducing breakdown voltage.
Innovation Solution
A multi-region field plate is introduced that partially overlaps the gate and the barrier offset layer, with sections of varying heights to minimize peak electric fields, combining a barrier offset layer and additional metal field plates to achieve a uniform electric field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a single layer of surface passivating insulator is made to minimize leakage current and gate to drain capacitance, then leakage current is reduced, but electron density in the channel decreases and drain field increases
Solution Approach 1:
The single insulator layer is segmented into multiple insulator layers with different thicknesses and material compositions. The first insulator layer (302) has greater thickness to minimize leakage and gate-drain capacitance, while the second insulator layer (304) has reduced thickness to maintain high electron density and provide low drain field, resolving the contradiction between leakage reduction and electron density maintenance
Solution Approach 2:
Different regions of the insulator structure are assigned different properties: the first insulator layer has greater thickness and is positioned to provide low leakage and low gate-drain capacitance, while the second insulator layer has reduced thickness and is positioned to provide high electron density and low drain field, allowing each region to optimize for its specific function
2Object-generated harmful factors
If the insulator thickness is increased to minimize leakage current, then leakage current is reduced, but the electric field at the corner of the barrier offset layer increases, reducing breakdown voltage
Solution Approach 1:
The insulator structure is segmented into multiple layers with varying thicknesses. The first insulator layer (302) has greater thickness to reduce leakage current, while the second insulator layer (304) has reduced thickness at the drain region to reduce the electric field concentration at the corner of the barrier offset layer, thereby maintaining high breakdown voltage
Solution Approach 2:
The insulator structure employs local quality variation where the first insulator layer provides thick insulation for leakage reduction in the gate region, while the second insulator layer provides thin insulation to reduce electric field concentration at the drain corner, optimizing both leakage current and breakdown voltage through spatially differentiated properties
3Reliability
If a multi-region field plate is introduced with varying heights, then electric field uniformity is improved and breakdown voltage increases, but device complexity increases
Solution Approach 1:
The field plate is segmented into multiple regions with different heights and positions. The multi-region field plate includes a first field plate region positioned over the first insulator layer and a second field plate region positioned over the second insulator layer, with varying heights to create a gradual electric field transition and minimize peak electric fields at critical corners, thereby increasing breakdown voltage through structured complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the breakdown voltage of GaN transistors by reducing electric fields at the corner of the gate and the edge of the barrier offset layer, improving device performance and reliability.
Implementation Method 1
A multi-region field plate is introduced that partially overlaps the gate and the barrier offset layer, with sections of varying heights to minimize peak electric fields, combining a barrier offset layer and additional metal field plates to achieve a uniform electric field
Data Source
AI summary
An enhancement mode GaN transistor that includes a multi-region field plate which partially overlaps the gate and partially overlaps a barrier offset layer. The multi-region field plate includes a section of increased height with respect to the channel layer over the portion of the gate nearest the drain contact, and a section of reduced height with respect to the channel layer over the edge or transition of the barrier offset layer, minimizing the peak electric field at the corner of the gate and at the edge or transition of the barrier offset layer.