GaN Transistor Field Plate Layout With CMP-Planarized Gate Patterning
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Solution Overview
Problem
Existing Group III nitride-based transistor devices face challenges in achieving precise gate and field plate structuring due to topography steps from Ohmic metal contacts, which affect photolithography processes and hinder the fabrication of short gate lengths and optimal gate-source distances, limiting device performance and manufacturability.
Innovation Solution
An Ohmic contact-first approach is employed, involving planarization of Ohmic metal before gate structure fabrication, using chemical mechanical polishing to create a planarized surface, enabling precise photolithography for shorter gate lengths and accurate positioning of the gate relative to the source contact, and incorporating a conductive redistribution structure for the gate and field plate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used without planarization, then Ohmic metal contacts can be formed first, but topography steps from the Ohmic metal contacts cause photolithography inaccuracies that prevent precise gate structuring and short gate lengths
Solution Approach 1:
The patent applies preliminary action by performing chemical mechanical polishing (CMP) planarization on the Ohmic metal contacts before fabricating the gate structure. This pre-flattening step removes topography steps that would otherwise cause photolithography inaccuracies, enabling precise gate structuring and short gate lengths while maintaining a manageable fabrication process
Solution Approach 2:
The patent introduces an intermediary planarization layer or process step between Ohmic metal formation and gate fabrication. The chemical mechanical polishing process acts as a mediator that eliminates surface irregularities, allowing subsequent photolithography to achieve high precision without being affected by underlying metal topography
2Speed
If gate length is reduced for improved device performance, then switching speed and frequency response improve, but photolithography precision requirements increase making fabrication more difficult
Solution Approach 1:
By performing CMP planarization before gate fabrication, the patent creates a flat surface that enables high-precision photolithography. This preliminary flattening allows the formation of shorter gate lengths with accurate dimensional control, thereby improving switching speed and frequency response without sacrificing manufacturability
3Reliability
If gate-source distance is optimized for device performance, then transistor characteristics improve, but precise positioning becomes more challenging due to topography variations
Solution Approach 1:
The patent performs planarization of the Ohmic metal contacts before defining the gate and source positions. This preliminary flattening eliminates topography-induced positioning errors, enabling precise control of gate-source distance and optimizing transistor characteristics for improved reliability and performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for reduced gate-source distance, improved critical dimension control, and enhanced device performance by minimizing topography-induced photolithography inaccuracies, facilitating cost-effective production on 200 mm wafers with high precision patterning.
Implementation Method 1
using chemical mechanical polishing to create a planarized surface
Data Source
AI summary
In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.