GaN Gate Stack with Composite Doping for Threshold Control
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Solution Overview
Problem
Conventional fluoride-based plasma treatment techniques for forming gate structures in semiconductor devices face control issues, particularly for enhanced mode (E-mode) and depletion mode (D-mode) transistors, necessitating a compound semiconductor gate structure and method for improved control.
Innovation Solution
A semiconductor structure comprising a silicon substrate with epitaxially grown III-V compound layers, including a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer, forming a two-dimensional electron gas (2-DEG) channel, with a gate stack incorporating a conductive metal layer, n-type and p-type doped semiconductor layers, and an aluminum nitride (AlN) layer, allowing for the formation of E-mode and D-mode transistors with adjustable threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If fluoride-based plasma treatment techniques are used for gate structure formation, then the gate structures can be formed, but control issues arise for devices having plural enhanced mode or depletion mode transistors
Solution Approach 1:
The patent applies local quality by creating different gate structures with specific doping configurations in different regions of the semiconductor device. Enhanced mode transistors receive gates with one doping configuration while depletion mode transistors receive gates with another configuration, allowing each region to have optimized properties for its specific function. This is achieved through selective doping processes that modify local electrical characteristics without affecting other regions.
Solution Approach 2:
The gate formation process is segmented into multiple discrete steps including selective doping, epitaxial growth, and patterned etching. Each step is independently controlled to achieve the desired threshold voltage characteristics for different transistor types. The gate structure itself is segmented into regions with different doping concentrations and compositions, allowing independent optimization of E-mode and D-mode device characteristics.
2Manufacturing precision
If conventional gate formation methods are used, then manufacturing is simpler, but manufacturing precision and control over threshold voltage are insufficient
Solution Approach 1:
The patent employs parameter changes by systematically varying doping concentrations, layer thicknesses, and material compositions to achieve precise control over threshold voltage. Different doping levels (e.g., 1e18 to 1e20 atoms/cm³), layer thicknesses (e.g., 5nm to 50nm), and material compositions (AlGaN with varying Al content) are used to tune the electrical characteristics of each gate structure for its intended function.
Solution Approach 2:
The gate structures utilize composite materials consisting of multiple semiconductor layers with different compositions and properties. The gate comprises stacked layers including doped GaN, AlGaN, and undoped GaN layers, each contributing specific electrical characteristics. This composite structure enables fine-tuned control of threshold voltage and carrier concentration that cannot be achieved with single-material gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables precise control over the threshold voltage and etching selectivity, resulting in enhanced performance and reliability of E-mode and D-mode transistors by leveraging the band gap discontinuity and piezo-electric effects in the GaN and AlGaN layers.
Implementation Method 1
leveraging the band gap discontinuity and piezo-electric effects in the GaN and AlGaN layers
Implementation Method 2
leveraging the band gap discontinuity and piezo-electric effects in the GaN and AlGaN layers
Data Source
AI summary
The present disclosure provides a semiconductor structure. The semiconductor structure includes a buffer layer on a substrate, an graded aluminum gallium nitride (AlGaN) layer disposed on the buffer layer, a gallium nitride (GaN) layer disposed on the graded AlGaN layer, a second AlGaN layer disposed on the GaN layer and a gate stack disposed on the second AlGaN layer. The gate stack includes one or more of a III-V compound p-doped layer, a III-V compound n-doped layer, an aluminum nitride (AlN) layer between the III-V compound p-doped and n-doped layers, and a metal layer formed over the p-doped, AlN, and n-doped layers. A dielectric layer can also underlie the metal layer.


