GaN HEMT Access Resistance Reduction via High-Concentration N-Type Doping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current GaN heterojunction field effect transistors face high access resistance and on resistance due to high junction resistance at the n-type impurity implantation regions and the channel interface, limiting their performance.
Innovation Solution
The implementation of n-type conductive layer regions with a high concentration of n-type impurity ions at the heterojunction interface, extending from the electron transit layer to the electron supply layer, reduces the junction resistance by increasing the n-type impurity concentration to 1×10^20 cm^-3 or more, thereby reducing access and on resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n-type impurity is implanted into the electron transit layer and electron supply layer to reduce access resistance and on resistance, then the junction resistance at the implantation regions increases, but the overall device performance deteriorates
Solution Approach 1:
The patent applies local quality by creating distinct n-type impurity concentration zones: a first n-type conductive layer region with high impurity concentration (1×10^20 cm^-3 or more) below the source and drain electrodes to reduce access resistance, and a second n-type conductive layer region with lower impurity concentration at the heterojunction interface to maintain low junction resistance. This spatial differentiation of impurity concentrations allows simultaneous optimization of both access resistance and junction resistance characteristics.
Solution Approach 2:
The patent utilizes parameter changes by precisely controlling the n-type impurity concentration at different locations and depths within the semiconductor structure. By adjusting the impurity concentration from 1×10^20 cm^-3 or more in the first region to lower concentrations in the second region, the patent optimizes the electrical characteristics to achieve both low access resistance and low junction resistance, thereby improving overall device performance.
2Reliability
If n-type impurity concentration is increased to reduce access resistance, then the on resistance decreases, but the junction resistance at the heterojunction interface increases
Solution Approach 1:
The patent implements local quality by establishing different n-type impurity concentration levels in vertically separated regions: the first n-type conductive layer region beneath the electrodes maintains high concentration (1×10^20 cm^-3 or more) for low on resistance, while the second n-type conductive layer region at the heterojunction interface maintains lower concentration to preserve low junction resistance. This vertical stratification of impurity concentrations resolves the contradiction between reducing on resistance and maintaining low junction resistance.
Solution Approach 2:
The patent resolves the contradiction by transitioning to a vertical dimensional arrangement of impurity concentration zones. Instead of uniform horizontal doping, the patent creates distinct vertical layers with different impurity concentrations, allowing the first region to optimize for low on resistance while the second region optimizes for low junction resistance, effectively decoupling these two parameters through spatial separation in the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly decreases the junction resistance, leading to lower access and on resistance in GaN heterojunction field effect transistors, enhancing their performance and operational efficiency.
Implementation Method 1
n-type conductive layer regions which are doped with an n-type impurity ion
Implementation Method 2
a concentration of the n-type impurity ion at a heterojunction interface of an electron transit layer part in each of the n-type conductive layer regions with the electron supply layer becomes 1×10^20 cm^-3 or more
Data Source
AI summary
A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.