GaN-HEMT Layout for Parasitic Inductance Reduction
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Solution Overview
Problem
The high-speed operation of GaN-HEMTs in power supply circuits increases parasitic inductance in wiring, leading to potential malfunctions.
Innovation Solution
A semiconductor device design featuring GaN-HEMTs and MOS-FETs in cascade connection with strategically positioned bypass capacitors and conductive patterns on an insulating substrate, where the GaN-HEMTs and MOS-FETs are disposed to minimize parasitic inductance by optimizing the layout and connections, including intersecting imaginary lines for the bypass capacitor paths and perpendicular connections for the gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GaN-HEMTs are applied to operate at high speed (exceeding 100 MHz), then power conversion efficiency is improved, but parasitic inductance in wiring causes malfunctions
Solution Approach 1:
The patent changes the spatial arrangement of components from conventional layouts to a configuration where bypass capacitors are positioned adjacent to GaN-HEMTs and connected via minimally extended wiring. This dimensional optimization of component placement reduces parasitic inductance paths while maintaining high-speed operation capability, resolving the contradiction between efficiency and reliability
Solution Approach 2:
The patent applies different wiring configurations to different parts of the circuit: bypass capacitors connected with minimally extended wiring to GaN-HEMTs, while other circuit elements maintain standard connections. This localized optimization of wiring quality reduces parasitic inductance at critical high-frequency nodes without compromising overall circuit functionality, addressing the reliability issue while preserving power conversion efficiency
Data Source
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AI summary
[Problem to be Solved] To suppress a malfunction of a power supply circuit having GaN-HEMTs. [Solution] A semiconductor device 1 of an embodiment includes an insulating substrate 2, conductive pattern parts 51, 52, 53, 54 and 55 formed on the insulating substrate, a GaN-HEMT 10 disposed on the conductive pattern part 51, and a GaN-HEMT 20 disposed on the conductive pattern part 52, wherein an imaginary line L1 of the GaN-HEMT 10 and an imaginary line L2 of the GaN-HEMT 20 intersect each other, a GaN gate electrode 23 of the GaN-HEMT 20 is electrically connected to the conductive pattern part 55 via a metal wire 6, and the metal wire 6 is perpendicular to a side S5 of the GaN-HEMT 20 and a conductive pattern side 55S of the conductive pattern part 55.