GaN HEMT Gate Stack with p-doped Layer for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-electron-mobility field-effect transistors, particularly those with gallium nitride-based structures, face issues with high gate leakage current, alignment constraints during metal electrode deposition, and limited isolating capacity when the gate is negatively biased, leading to increased electrical consumption and potential hole injection into the electron gas layer.
Innovation Solution
A normally-off high-electron-mobility field-effect transistor design featuring a gate stack with a p-doped semiconductor element, a dielectric layer, and a conductive electrode, where the dielectric layer reduces gate leakage and allows self-alignment, decreasing the required gate length and increasing the threshold voltage without increasing gate leakage current, and includes a dielectric layer to limit dopant diffusion and enhance electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a current-limiting layer is used to limit gate leakage, then gate leakage is reduced, but the isolating capacity is limited when the gate is negatively biased and holes may be injected into the electron gas layer when the gate is positively biased
Solution Approach 1:
The patent employs a composite gate stack structure comprising multiple layers with different materials and doping types: a first doped layer (p-type GaN), a second undoped layer (GaN), and a third doped layer (p-type AlGaN). This composite structure combines the advantages of different material properties to achieve both low gate leakage and high isolating capacity, while preventing hole injection into the electron gas layer.
2Ease of operation
If metal electrode is deposited on lower layers of the stack, then gate control is achieved, but alignment constraints result in a relatively long gate length
Solution Approach 1:
The patent transitions from planar metal electrode deposition to a vertical gate stack architecture. The gate control is achieved through the vertical stacking of doped and undoped semiconductor layers, allowing the gate to effectively control the channel without requiring long lateral extensions. This dimensional change from 2D planar to 3D vertical structure enables shorter gate lengths while maintaining effective gate control.
3Loss of energy
If the gate stack is designed to reduce gate leakage, then electrical consumption is reduced, but the device complexity increases
Solution Approach 1:
The patent reduces gate leakage by changing the doping parameters of the semiconductor layers. The first layer is doped with a first type (p-type) and the third layer is doped with the same type, while the second layer remains undoped. By adjusting doping concentrations and layer thicknesses, the patent achieves low gate leakage current without requiring overly complex structural designs. The parameter optimization allows simple yet effective leakage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces gate leakage, decreases the gate length, and enhances the threshold voltage and electrostatic control of the channel, while maintaining high electron mobility and density, thus improving the performance and reliability of the transistor.
Implementation Method 1
a p-doped semiconductor element arranged below the conductive electrode and arranged in contact with an upper face of the layer made of AlGaN
Implementation Method 2
a dielectric layer arranged between the conductive electrode and the element made of semiconductor material
Implementation Method 3
the superposition of two semiconductor layers having different bandgaps which form a quantum well at their interface. Electrons are confined in this quantum well in order to form a two-dimensional electron gas
Implementation Method 4
The layer made of p-doped GaN is intended to interrupt the electron gas layer between the source electrode and the drain electrode in the absence of bias on the various electrodes
Data Source
AI summary
A high-electron-mobility field-effect transistor includes a superposition of first and second layers of semiconductor materials so as to form an electron gas layer and includes a gate stack arranged on the superposition. The gate stack includes a conductive electrode and an element made of p-doped semiconductor material, arranged between the conductive electrode and the superposition. The gate stack includes a first dielectric layer arranged between the conductive electrode and the element made of semiconductor material. The element made of semiconductor material, the first dielectric layer, and the conductive electrode have aligned lateral flanks.