GaN Transistor Gate Insulator Impurity Peaks

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Solution Overview

Problem

GaN-based semiconductor transistors face issues with current collapse and threshold voltage variation due to electron trap levels at the interface between the nitride semiconductor layer and the insulating layer, leading to poor reliability.

Innovation Solution

Incorporating an oxide or oxynitride film with specific impurities like boron, gallium, aluminum, and carbon in the gate insulating layer, with concentration peaks close to the nitride semiconductor layer to reduce electron trap levels and prevent current collapse.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If GaN-based semiconductor is used to improve breakdown voltage and reduce on-resistance, then the trade-off relationship between breakdown voltage and on-resistance is improved, but current collapse and threshold voltage variation occur due to electron trap levels at the interface

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidelectron trap levels
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

An insulating layer comprising an oxide film or oxynitride film is introduced as an intermediary between the nitride semiconductor layer and the gate electrode. This insulating layer acts as a mediator that reduces electron trap levels at the interface, thereby preventing current collapse and threshold voltage variation while allowing the GaN-based semiconductor to maintain its high breakdown voltage and low on-resistance characteristics

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the interface characteristics by changing the chemical composition and physical properties of the insulating layer. Specifically, the oxide film or oxynitride film with specific impurity concentrations (first peak within 5 nm and second peak within 20 nm from the interface) alters the electrical parameters at the interface, reducing electron trap levels and improving device reliability

Inventive Principle:
Principle #35Parameter changes

2Power

If high drain voltage is applied to GaN-based semiconductor transistor, then power handling capability is improved, but current collapse occurs due to electron trap levels

Engineering Contradiction:
Improvepower handling capabilityVSAvoidcurrent collapse resistance
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The insulating layer serves as a protective intermediary that shields the nitride semiconductor layer from direct contact with the gate electrode, thereby reducing electron trap levels that cause current collapse during high power operation. This allows the transistor to maintain stable performance under high drain voltage conditions

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If simple insulating layer is used at the interface, then device structure is simplified, but electron trap levels remain high causing threshold voltage variation

Engineering Contradiction:
Improveinterface structure complexityVSAvoidthreshold voltage stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent employs a composite insulating layer structure comprising an oxide film or oxynitride film with specific impurity compositions. This composite material approach achieves effective reduction of electron trap levels and threshold voltage stabilization without significantly increasing device structure complexity, as the insulating layer can be formed in a single step with controlled impurity distribution

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces electron trap levels, preventing current collapse and threshold voltage variations, thereby enhancing the reliability of GaN-based semiconductor devices.

Implementation Method 1

An insulating layer which comprises an oxide film or an oxynitride film and has a specific impurity concentration distribution is formed over a nitride semiconductor layer. A first peak of a concentration distribution of the at least one impurity in the insulating layer is present in the oxide film or the oxynitride film. A second peak of a concentration distribution of carbon in the insulating layer is present in the oxide film or the oxynitride film.

Methodology Applied
Scientific EffectImpurity concentration distribution effect:

Implementation Method 2

the oxide film or the oxynitride film includes at least one impurity selected from the group consisting of boron (B), gallium (Ga), aluminum (Al), and indium (In) and carbon (C)... effectively reduces electron trap levels, preventing current collapse and threshold voltage variations

Methodology Applied
Scientific EffectElectron trap level reduction:

Data Source

PatentUS9954092B2Semiconductor device, power circuit, and computer
Publication Date: 2018.04.24 KK TOSHIBA
  • US9954092B2 patent drawing
  • US9954092B2 patent drawing
  • US9954092B2 patent drawing

AI summary

A semiconductor device according to an embodiment includes a nitride semiconductor layer and an insulating layer including an oxide film or an oxynitride film that contacts with the nitride semiconductor layer. The oxide film or the oxynitride film includes at least one impurity selected from the group consisting of boron (B), gallium (Ga), aluminum (Al), and indium (In) and carbon (C). A first peak of a concentration distribution of the at least one impurity in the insulating layer is present in the oxide film or the oxynitride film. A second peak of a concentration distribution of carbon in the insulating layer is present in the oxide film or the oxynitride film. A distance between the first peak and the nitride semiconductor layer is equal to or less than 5 nm, and a distance between the second peak and the nitride semiconductor layer is equal to or less than 5 nm.