GaN Isolation Structure Using Gate Patterns
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Solution Overview
Problem
Existing methods for fabricating isolation structures in gallium nitride (GaN) semiconductor devices require dedicated masks, result in high leakage current, and suffer from resistivity degradation, increasing costs and reducing the effectiveness of the isolation region.
Innovation Solution
A method for forming an isolation region between transistor devices using gate structures and spaces on a shared film stack, eliminating the need for dedicated masks and reducing leakage current by using the same process sequences as the gate contacts, thereby lowering processing costs and enhancing isolation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated masks are used to form isolation areas by etching or ion-implantation, then isolation structures can be formed, but processing costs increase and device complexity increases
Solution Approach 1:
The patent combines the gate structure formation process with the isolation structure formation process by using the same gate pattern to define both the gate electrode positions and the isolation area boundaries. This eliminates the need for separate dedicated masks for isolation, reducing processing steps and device complexity while maintaining effective electrical isolation between adjacent devices.
Solution Approach 2:
The gate pattern serves dual purposes: defining the gate electrode locations and simultaneously defining the isolation areas between devices. This multi-functional approach eliminates the need for separate isolation masks, reducing processing complexity while achieving the same isolation effectiveness.
2Reliability
If isolation areas are formed by removing conductive layers through etching, then electrical isolation between devices is achieved, but leakage current increases
Solution Approach 1:
The patent applies a dielectric material to the exposed semiconductor surface in the isolation areas before final processing steps. This dielectric layer serves as a protective cushion that prevents leakage current paths from forming at the etched surfaces, while maintaining the electrical isolation function of the isolation structures.
3Reliability
If ion-implantation is used to convert conductive layers into insulating layers, then isolation structures are formed, but resistivity degrades after high temperature processing
Solution Approach 1:
The patent changes the material parameter by using a dielectric material layer in the isolation regions instead of relying on ion-implanted regions. This dielectric material maintains its insulating properties through high temperature processing without the resistivity degradation that occurs with ion-implantation methods, ensuring stable isolation characteristics.
4Reliability
If isolation areas are separated by space LISO, then electrical isolation between devices is achieved, but device area increases
Solution Approach 1:
The patent merges the gate structure with the isolation structure by using the gate pattern itself to define the isolation areas. This integration eliminates the need for additional separation spaces between devices, as the gate structures and their associated dielectric layers provide both the functional gate elements and the electrical isolation, thereby reducing the overall chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced leakage current and lower processing costs without the need for dedicated masks, improving the isolation efficiency and maintaining the integrity of the isolation region, supporting voltages of 50-200V per μm in GaN-based materials.
Implementation Method 1
the gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device
Data Source
AI summary
An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.