Lift-off Process for GaN Devices on Engineered Substrates
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Solution Overview
Problem
Wide band gap semiconductor devices, such as gallium nitride (GaN), face manufacturing challenges due to lattice mismatch and different coefficients of thermal expansion between the GaN layers and carrier substrates, leading to defects, strains, and increased costs.
Innovation Solution
The method involves forming solid state devices on engineered substrates with a coefficient of thermal expansion matched to the epitaxial layers, using a sacrificial layer and etching chemicals to separate the substrate from the devices, allowing for reuse and reducing stress and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GaN layers are formed on a carrier substrate with different lattice structure, then epitaxial growth can proceed, but lattice mismatch creates defects, dislocations, and strains that negatively impact device yields and performance
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the carrier substrate and the GaN epitaxial layers. This buffer layer has a lattice structure that gradually transitions from the substrate to the GaN layers, mediating the lattice mismatch and reducing dislocation propagation. The buffer layer acts as a transition zone that allows epitaxial growth to proceed while minimizing defects in the active device regions.
Solution Approach 2:
The patent modifies the lattice parameter and coefficient of thermal expansion by selecting specific carrier substrate materials and designing multi-layer buffer structures with graded composition. By changing the lattice parameters of intermediate layers, the patent reduces the effective lattice mismatch between the substrate and GaN layers, thereby reducing dislocation density and improving device performance.
2Ease of manufacture
If thermal processing is performed for GaN epitaxial growth, then the GaN layers can be formed, but the different coefficients of thermal expansion may crack or delaminate the GaN or break the carrier substrate
Solution Approach 1:
The patent employs a composite multi-layer structure consisting of the carrier substrate, buffer layers with intermediate thermal expansion coefficients, and the GaN epitaxial layers. This composite structure distributes the thermal stress across layers with progressively matching thermal expansion properties, preventing stress concentration that would cause cracking or delamination during thermal processing.
Solution Approach 2:
The patent selects carrier substrate materials and buffer layer compositions with coefficients of thermal expansion that closely match the GaN layers. By changing and matching the thermal expansion parameters of each layer, the patent minimizes thermal stress during epitaxial growth and subsequent processing, preventing cracking and delamination while maintaining structural integrity.
3Productivity
If the different coefficients of thermal expansion are not addressed, then manufacturing can proceed, but the substrate wafer size is restricted and manufacturing cost cannot be reduced
Solution Approach 1:
The patent changes the thermal expansion parameters of the carrier substrate and buffer layers to match the GaN epitaxial layers. By selecting substrates and designing buffer structures with CTE values close to GaN, the patent enables larger substrate wafer sizes to be used without experiencing thermal mismatch failures, thereby increasing productivity and reducing manufacturing cost per device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces stress-induced defects, enables the formation of higher quality, thicker epitaxial layers on larger substrates, and allows for cost-effective reuse of substrates, improving device performance and reducing manufacturing time and costs.
Implementation Method 1
flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer
Data Source
AI summary
A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an engineered layer encapsulating the polycrystalline substrate, forming a sacrificial layer coupled to the engineered layer, joining a solid state device structure to the sacrificial layer, forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer, flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.