GaN Dual Field Plate Device With Multi-Region Structure
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Solution Overview
Problem
Conventional gallium nitride transistor devices face challenges in achieving high voltage and high frequency capabilities while maintaining low dynamic drain to source on-resistance (Rdson) and breakdown voltage, as increasing operating voltage can lead to increased gate and drain leakage currents and reduced device reliability.
Innovation Solution
A multi-region field plate structure is formed using an inter-layer dielectric (ILD) stack with intermediate dielectric etch stop layers, which reduces dynamic Rdson by creating multiple distances between the field plate electrode and the device channel, thereby reducing peak electric field intensity and enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If operating voltage is increased to meet high voltage capability requirements, then breakdown voltage is improved, but gate and drain leakage currents increase and device reliability deteriorates
Solution Approach 1:
The field plate structure creates different electric field distributions in different regions: a first field plate region with a first distance from the channel and a second field plate region with a second distance from the channel. This local differentiation allows optimized electric field control in high-stress regions without compromising overall device reliability, enabling high breakdown voltage while controlling leakage currents.
Solution Approach 2:
The invention introduces a vertical dimension to field plate design by creating multi-level field plate regions at different distances from the channel. This three-dimensional field plate structure allows independent optimization of electric field control in different vertical zones, achieving high breakdown voltage while maintaining low leakage currents through spatially differentiated field management.
2Device complexity
If conventional single field plate structure is used, then device structure is simple, but dynamic drain to source on-resistance cannot be effectively reduced
Solution Approach 1:
The field plate is segmented into multiple regions: a first field plate region extending from the gate to a first distance from the drain, and a second field plate region extending from the gate to a second distance from the drain. This segmentation allows each region to be optimized for specific functions, effectively reducing dynamic Rdson through differentiated electric field control in various spatial zones.
Solution Approach 2:
Different field plate regions are assigned different distances from the channel to optimize local electric field characteristics. The first field plate region provides one level of field control while the second field plate region provides another level, allowing localized optimization of dynamic Rdson without requiring complex multi-material structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-region field plate structure effectively reduces dynamic Rdson and improves breakdown voltage, providing superior performance in high voltage switching applications while simplifying layout requirements and integrating seamlessly with existing fabrication processes.
Implementation Method 1
reduces peak electric field intensity by creating multiple distances between the field plate electrode and the device channel
Implementation Method 2
an inter-layer dielectric (ILD) stack with intermediate dielectric etch stop layers
Data Source
AI summary
A low leakage current transistor (2) is provided which includes a GaN-containing substrate (11-14) covered by a passivation surface layer (17) in which a T-gate electrode with sidewall extensions (20) is formed and coated with a multi-level passivation layer (30-32) which includes an intermediate etch stop layer (31) which is used to define a continuous multi-region field plate (33) having multiple distances between the bottom surface of the field plate 33 and the semiconductor substrate in the gate-drain region of the transistor.