GaN Transistor Gate Segmentation for Leakage Control
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Solution Overview
Problem
Existing semiconductor devices, particularly those using gallium nitride (GaN), face challenges in controlling charge density and mobility of electrons in two-dimensional electron gas (2DEG) with high gate leakage and negative gate bias requirements, which affect the performance of transistors like high power field-effect transistors and high frequency transistors.
Innovation Solution
The implementation of a GaN-based transistor structure that combines enhancement-mode and depletion-mode devices across a drift region, utilizing P-type layers and Schottky barriers to control electron flow, with a gate electrode coupled to each P-type layer and insulated from depletion-mode devices, allowing for alternating patterns of enhancement-mode and depletion-mode structures to manage electron flow efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conventional GaN transistor structure is used, then high power and high frequency performance is achieved, but gate leakage increases and negative gate bias requirement increases
Solution Approach 1:
The gate region is segmented into multiple independent gate electrodes (first gate electrode, second gate electrode, third gate electrode) that can be independently controlled. This segmentation allows different gate voltages to be applied to different regions, enabling precise control of electron flow while reducing overall gate leakage and lowering the negative gate bias requirement.
Solution Approach 2:
Different regions of the gate structure are given different properties: the first gate electrode controls the drift region, the second gate electrode controls the barrier layer, and the third gate electrode provides additional control. This local differentiation allows optimization of electron mobility in specific regions while maintaining low gate leakage overall.
2Power
If a conventional GaN transistor structure is used, then high power field-effect transistor performance is achieved, but negative gate bias requirement increases
Solution Approach 1:
The segmented gate structure with multiple independently controllable electrodes eliminates the need for high negative gate bias by allowing positive or zero bias to be applied to specific gate regions that control electron flow, thereby simplifying the operating conditions while maintaining high power performance.
Solution Approach 2:
The invention changes the electrical parameters (gate voltages) of different gate regions independently, allowing the transistor to operate with reduced or eliminated negative gate bias requirements while maintaining high power performance through optimized electron control in each region.
3Reliability
If enhancement-mode structures with p-type layers are used, then electron mobility is improved, but device complexity increases
Solution Approach 1:
The device is segmented into distinct functional regions (drift region, barrier layer, multiple gate electrodes) where enhancement-mode structures with p-type layers are strategically placed only where needed to improve electron mobility, rather than throughout the entire device, thus limiting complexity increase to specific high-value regions.
Solution Approach 2:
Enhancement-mode structures with p-type layers are applied locally in specific regions (such as under the second gate electrode in the barrier layer) where electron mobility improvement is most critical, rather than uniformly throughout the device, achieving performance enhancement with minimal added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the on-resistance of transistors by allowing electron flow across the entire width of the gate region, achieving a lower threshold voltage and improved electron mobility with reduced gate leakage, enabling efficient operation in a wide voltage range from 10 Volts to 40 Volts.
Implementation Method 1
The gate region includes at least one depletion-mode structure and at least one enhancement-mode structure
Data Source
AI summary
A gallium nitride transistor includes a substrate on which a source region, a drain region, a drift region and a gate region are defined. The drift region extends between the source region and the drain region. The gate region includes a combination of enhancement-mode and depletion-mode devices that are positioned across the drift region and are used together to control charge density and mobility of electrons in the drift region with a relatively low threshold voltage (Vth). Enhancement-mode devices are formed using a P-type layer disposed on the substrate and coupled to a gate electrode.