Enhancement Mode GaN Transistor Quantum Well Barrier
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Solution Overview
Problem
GaN high electron mobility transistors tend to be normally on due to high-concentration two-dimension electron gas, limiting their application to enhancement mode or normally-off transistor devices, and existing manufacturing processes result in non-uniform electrical properties and unstable gate thickness.
Innovation Solution
An enhancement mode GaN transistor device with a quantum well structure is developed, featuring a GaN layer, a quantum well structure, a gate, a source, a drain, and a first barrier layer, where the quantum well structure is disposed on the GaN layer, and the gate is positioned on the quantum well structure, utilizing a re-grown barrier layer and anti-polarization layers to control electron gas concentration and energy levels, enabling normally-off operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-concentration two-dimension electron gas is formed in GaN HEMT, then transmission characteristics and output current density are improved, but the device becomes normally on and cannot be applied to enhancement mode transistor devices
Solution Approach 1:
The patent changes the electrical parameters of the GaN layer by controlling the concentration of silicon dopants within a specific range (1×10^16 to 1×10^18 atoms/cm³) and adjusting the thickness of the AlGaN barrier layer (15-30 nm). These parameter changes reduce the two-dimension electron gas concentration to below 1×10^13 cm⁻², transforming the device from normally-on to normally-off mode while maintaining acceptable transmission characteristics.
Solution Approach 2:
The patent applies local quality by creating a heterostructure with different material compositions: the AlGaN barrier layer has aluminum content x ranging from 0.2 to 0.4, while the GaN layer has controlled silicon doping. This local variation in material properties enables spatial control of electron gas distribution, achieving normally-off operation in specific regions while maintaining overall device performance.
2Ease of manufacture
If existing manufacturing processes are used for enhancement mode GaN devices, then device fabrication is achieved, but non-uniform electrical properties and unstable gate thickness result
Solution Approach 1:
The patent applies preliminary action by pre-controlling the silicon dopant concentration in the GaN layer and the aluminum content in the AlGaN barrier layer before device operation. These preliminary compositional controls establish a foundation that ensures uniform electrical properties and stable gate characteristics throughout the manufacturing process, preventing variations rather than correcting them later.
Solution Approach 2:
The patent implements feedback by establishing specific target ranges for dopant concentrations and layer thicknesses that can be measured and controlled during manufacturing. By setting quantitative parameters (silicon concentration 1×10^16 to 1×10^18 atoms/cm³, AlGaN thickness 15-30 nm), the manufacturing process can monitor and adjust conditions to maintain electrical property uniformity and gate thickness stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves improved performance and reliability by providing confined carrier levels and anti-polarization characteristics, allowing for enhanced current density and conforming to normally-off transistor requirements, while the controlled etching process optimizes transistor quality and flexibility.
Implementation Method 1
the quantum well structure is disposed on the upper surface of the GaN layer... providing confined carrier levels
Implementation Method 2
Gallium Nitride high electron mobility transistors (GaN HEMT)... form high-concentration two-dimension electron gas (2DEG)
Data Source
AI summary
An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.