Gapper and Multi-Modulus Divider for Higher-Frequency Synthesis
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Solution Overview
Problem
Conventional gapper-based frequency synthesizers are limited to generating output signals with a frequency lower than the input signal, making it difficult to achieve higher output frequencies required in applications such as converting from STS-192 to OTU2, where a frequency change from 622.08 MHz to 669.326 MHz is needed.
Innovation Solution
An integrated circuit with a gapper and a multi-modulus divider that generates a gapped signal by removing pulses from the input signal, allowing the frequency ratio of the output signal to be greater than the input signal, using a sequence of divide ratios and gapping control signals to achieve the desired frequency conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional gapper-based frequency synthesizer is used, then the output signal frequency is lower than the input signal frequency, but this limits the ability to achieve higher output frequencies required in applications such as converting from STS-192 to OTU2
Solution Approach 1:
The patent employs a multi-modulus divider that can dynamically switch between different divide ratios (N and N+1) based on control signals. This dynamic adjustment capability allows the frequency synthesizer to adaptively change the frequency division factor, enabling both frequency reduction (when D>1) and frequency increase (when D<1) operations, thereby resolving the contradiction between output frequency and adaptability
Solution Approach 2:
The invention changes the division ratio parameter of the frequency divider from a fixed value to a variable value that can be selectively switched between N and N+1. By controlling which divide ratio is applied at different time periods, the system can achieve an average division ratio that corresponds to any rational frequency ratio D=P/Q, enabling flexible frequency conversion in both directions
2Reliability
If a gapper is used to generate a gapped signal with missing clock edges, then the average frequency is reduced for synchronization, but significant jitter is introduced that is not tolerated by downstream consumer circuitry
Solution Approach 1:
The patent introduces a jitter attenuating PLL as an intermediary component between the gapper and the output stage. The PLL receives the gapped signal with jitter, processes it through its phase detection and feedback mechanism, and produces a clean output signal that maintains the same average frequency as the gapped signal but with the jitter component significantly attenuated
Solution Approach 2:
The invention separates the jitter attenuation function from the frequency synthesis function by extracting the jitter component removal process through the PLL. The gapper handles only the frequency ratio adjustment by generating gapped signals, while the PLL independently handles the jitter removal, allowing each component to specialize in its respective function
3Speed
If the frequency ratio D is less than 1 (output frequency higher than input frequency), then higher output frequencies can be achieved, but conventional gapper-based synthesizers are limited to D>1
Solution Approach 1:
The multi-modulus divider dynamically switches between divide ratios N and N+1 based on control signals generated by the DSM. This dynamic switching enables the system to achieve effective frequency multiplication (D<1) by strategically applying different division factors over time periods, thereby extending the frequency synthesizer's capability beyond the conventional D>1 limitation
Solution Approach 2:
The invention uses periodic switching of the divide ratio according to a predetermined pattern generated by the DSM. By periodically alternating between dividing by N and N+1 over specific time intervals, the system achieves an average division ratio that corresponds to the desired frequency ratio D=P/Q, enabling flexible frequency conversion including cases where D<1
Data Source
AI summary
Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.