Gate-All-Around Semiconductor Device Reducing Leakage Currents
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Solution Overview
Problem
As semiconductor devices integrate to smaller sizes, they face issues like short channel effects, increased gate-induced drain leakage (GIDL), and gate leakage currents due to the close proximity of source/drain and gate electrodes, which existing technologies struggle to mitigate effectively.
Innovation Solution
A gate-all-around (GAA) type semiconductor device design featuring a nanowire channel with a reduced gate electrode size and an insulation layer pattern between the gate electrode and source/drain layers, reducing the contact area and increasing the distance between them to minimize GIDL and gate leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length of the MOS transistor is reduced to increase integration degree, then productivity and integration are improved, but short channel effect increases and channel driving capability deteriorates
Solution Approach 1:
The gate electrode transitions from a planar structure to a three-dimensional gate-all-around structure that completely surrounds the nanowire channel. This dimensional change allows the gate to control the channel from all directions (top, bottom, and sidewalls), providing superior electrostatic control and reducing short channel effects even at reduced channel lengths, thus maintaining channel driving capability while enabling higher integration.
Solution Approach 2:
The gate electrode is configured to completely surround and enclose the nanowire channel in a nested arrangement. This nested structure allows the gate to exert control over the channel from multiple directions simultaneously, enhancing the electric field distribution and improving carrier control without requiring larger device dimensions, thereby maintaining performance at reduced channel lengths.
2Area of stationary object
If the source/drain region and gate electrode are closely disposed to reduce device size, then area is reduced, but high electric field is generated and gate induced drain leakage increases
Solution Approach 1:
An insulation layer pattern is introduced as an intermediary between the source/drain region and the gate electrode. This insulation layer acts as a physical barrier that prevents direct contact and reduces the electric field interaction between these regions, thereby suppressing gate induced drain leakage while allowing the device to maintain a compact footprint.
Solution Approach 2:
The insulation layer pattern is strategically positioned only in specific locations where source/drain regions approach the gate electrode, rather than uniformly throughout the device. This localized application of insulation provides targeted suppression of GIDL at critical interfaces while maintaining overall device compactness and not unnecessarily increasing the total device area.
3Ease of manufacture
If the gate electrode makes contact with the source/drain region at a broad area to simplify structure, then manufacturing is easier, but gate leakage current increases
Solution Approach 1:
The insulation layer pattern serves as an intermediary that prevents direct contact between the gate electrode and source/drain region. This intermediary layer is integrated into the manufacturing process through standard deposition and patterning steps, maintaining ease of manufacture while effectively blocking leakage current paths that would otherwise occur at broad contact areas.
Solution Approach 2:
The gate electrode structure is segmented by the insulation layer pattern, creating distinct regions where the gate contacts the channel but is isolated from direct contact with source/drain regions. This segmentation allows the gate to maintain its functional simplicity while preventing leakage current, achieving both ease of manufacture and reduced gate leakage.
Data Source
AI summary
The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.