Gate Cap Protection via Oxide Layer in Integrated Circuits
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Solution Overview
Problem
Conventional methods for forming electrical interconnects in semiconductor integrated circuits often compromise the gate electrode structure due to susceptibility of nitride caps to etch-through during via etching, leading to reliability concerns and performance impacts.
Innovation Solution
A protecting layer with a lower etch rate than silicon nitride and oxide is deposited over recessed surfaces of sidewall spacers and caps, shielding them during via etching through dielectric layers to prevent exposure and damage to the gate electrode structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a nitride cap is formed over the gate electrode structure prior to via etching, then the gate electrode structure is protected during initial processing, but the nitride cap is susceptible to etch-through during via etching through oxide and nitride dielectric layers
Solution Approach 1:
The patent applies a multi-layer composite protection structure consisting of a nitride cap layer combined with an oxide protection layer. This composite structure leverages the etch selectivity between different materials - the oxide layer has significantly lower etch rate in nitride etchants compared to nitride itself, creating a protective barrier that prevents etch-through while allowing via formation through the dielectric layers.
Solution Approach 2:
The oxide protection layer serves as an intermediary protective element between the nitride cap and the etchant. This intermediary layer is specifically designed to be resistant to nitride etchants, thereby mediating the interaction between the etchant and the nitride cap, preventing direct contact and potential etch-through damage to the gate electrode structure.
2Reliability
If additional layers are added over the dielectric layer and nitride cap to protect during via formation, then protection is provided, but the additional layers must still be etched during via formation such that nitride cap etch-through may still be a concern
Solution Approach 1:
The patent changes the material parameter of the protection layer from nitride to oxide, exploiting the significant difference in etch rates between these materials. The oxide layer has a much lower etch rate in nitride etchants, providing inherent protection without requiring additional complex protective layers. This parameter change (material selection) simplifies the overall structure while maintaining protection.
3Ease of manufacture
If conventional oxide etchants are used to etch through dielectric layers, then via formation is achieved, but oxide etchants also etch nitrides albeit at a significantly lesser rate causing potential etch-through
Solution Approach 1:
The patent applies beforehand cushioning by forming an oxide protection layer over the nitride cap prior to via etching. This pre-formed protective layer acts as a cushion or buffer that absorbs the etching action, preventing direct exposure of the nitride cap to the etchant and eliminating the need for additional protective measures during the etching process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protecting layer effectively shields the gate electrode structure from etchants, preventing etch-through and maintaining transistor performance while enabling proper formation of electrical interconnects, thus enhancing device reliability and performance.
Implementation Method 1
A protecting layer having a lower etch rate in nitride etchants and oxide etchants than silicon nitride and silicon oxide, respectively
Data Source
AI summary
Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.