Gate Parasitic Capacitance Calibration Using Segmented MOS Test Structures
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Solution Overview
Problem
Existing technologies face challenges in accurately calibrating gate parasitic capacitance due to the complexity of the parasitic capacitance in front-end-of-line metal interconnect structures, which deviates from actual results.
Innovation Solution
A test structure and method are provided, including multiple capacitance test structures and a series of steps to measure and calibrate parasitic capacitances such as Cgm, Cco, and Cf, ensuring consistency between simulation and actual measurement results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test methods measure Cco+Cf together and subtract Cf without considering contact hole arrangement, then the measurement process is simple, but the calibration accuracy deviates from actual results
Solution Approach 1:
The patent segments the gate parasitic capacitance into distinct components (Cco, Cf, Cgd) by designing separate test structures for each. The first test structure measures Cco+Cf+Cgd, the second measures only Cf+Cgd, and the third measures only Cgd. This segmentation allows accurate extraction of Cco by subtraction while accounting for contact hole arrangements, resolving the accuracy issue without requiring complex single-structure measurements
Solution Approach 2:
The patent introduces control groups (test structures with different contact hole arrangements) as intermediaries to isolate and measure the influence of contact holes on capacitance. By comparing test structures with and without contact holes, or with different contact hole configurations, the method accurately separates Cco from Cf, serving as a mediator to achieve precise calibration
2Measurement precision
If multiple test structures with different contact hole arrangements are designed, then the calibration accuracy improves, but the device complexity increases
Solution Approach 1:
The patent applies local quality by designing test structures with specific, localized variations in contact hole arrangements while keeping other parameters consistent. Each test structure has a defined local configuration (presence/absence of contact holes, specific spacing) that isolates the effect of contact holes on capacitance, enabling accurate measurement without requiring complete redesign of the entire test structure
Solution Approach 2:
The patent uses partial action by designing test structures that include only the necessary elements for measuring specific capacitance components. Rather than creating completely different test structures for each capacitance type, the method uses incremental modifications (adding/removing contact holes) to isolate specific effects, reducing overall complexity while maintaining accuracy
3Reliability
If contact holes are present in source/drain regions, then the test structure is complete, but the separation of Cco and Cf becomes difficult
Solution Approach 1:
The patent applies inversion by measuring the capacitance with contact holes present (Cco+Cf+Cgd) and then measuring without contact holes (Cf+Cgd), subtracting the second from the first to obtain Cco. Instead of trying to directly measure Cco in isolation, the method measures the total and subtracts the components, reversing the conventional approach and achieving accurate separation
Data Source
AI summary
This application provides a test structure and a method for calibrating gate parasitic capacitance. A first test structure can calibrate a dimension and thickness table related to a first metal layer in an ITF file. A second test structure is formed by an MOS structure after removing contact holes in source/drain regions, and this structure is used for calibrating gate dimension and thickness values in the ITF file. A third test structure is formed by the MOS structure after removing metal interconnect lines in source/drain regions, removing shallow doped source/drain regions composed of first conductive type lightly-doped regions, and this structure is used for calibrating tables related to capacitance Cco and Cf in the ITF file. A fourth test structure is an MOS structure, and its actual capacitance test result is compared with a simulation result to ensure that the gate parasitic capacitance conforms to the model simulation.