Gate Contact Opening Doping for Defect-Controlled Semiconductor Scaling
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating electronic components efficiently while maintaining performance and reducing defects, particularly in the formation of isolation regions and gate structures.
Innovation Solution
A pseudo bottom-up plug process is employed to form fins and isolation regions, using masking layers and etching processes to create trenches, followed by dielectric filling and recessing, and subsequent deposition of gate stacks and contacts, enhancing the integration density and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but manufacturing precision and defect control become more difficult
Solution Approach 1:
The patent divides the gate electrode formation into multiple segments: a first gate electrode layer is formed initially, then a second gate electrode layer is formed after source/drain region formation. This segmentation allows each layer to be optimized independently for their specific functions, enabling better control at reduced feature sizes while maintaining high integration density.
Solution Approach 2:
The first gate electrode layer is formed preliminarily before the source and drain regions are fully defined. This preliminary action establishes a foundation that guides subsequent processing steps, ensuring that when features are scaled down, the alignment and positioning remain precise throughout the manufacturing process.
2Ease of manufacture
If conventional gate electrode formation is used to simplify the process, then manufacturing is easier, but interfacial defects increase between gate and source/drain regions
Solution Approach 1:
The gate electrode is segmented into two distinct layers formed at different stages. The first layer is formed before source/drain regions, and the second layer is formed after. This segmentation ensures that each interface (gate-source and gate-drain) is created under optimal conditions, minimizing interfacial defects while maintaining reasonable process complexity.
Solution Approach 2:
The first gate electrode layer serves as a preliminary structure that defines the gate region boundaries before source and drain formation. This preliminary action creates well-defined interfaces that reduce defect formation, and the subsequent second layer completes the gate structure with proper electrical properties.
Data Source
AI summary
Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.