Gate Contact Placement in Integrated Circuit Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuits are scaled down, the increased gate resistance in RF transistors reduces the maximum oscillation frequency and RF cutoff frequency, primarily due to the conventional placement of gate contacts over the STI region rather than the active region, leading to higher gate resistance.
Innovation Solution
The method involves lowering the height of source/drain contacts within a dielectric layer to be below the gate conductor height and forming a conductor that extends over and contacts the gate conductor without touching the source/drain contacts, thereby placing the gate contact within the active region closer to both ends of the gate stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate contacts are formed over STI region, then manufacturing is simplified, but gate resistance increases
Solution Approach 1:
The patent transitions from planar gate contact formation to three-dimensional gate contact formation by extending the gate contact laterally along the gate stack. This dimensional change allows the gate contact to reach closer to both ends of the gate stack while maintaining manufacturability through standard lithography and etching processes.
Solution Approach 2:
The gate contact is formed to extend laterally before final metallization completion,预先 positioning it to contact both ends of the gate stack. This preliminary action reduces gate resistance before subsequent processing steps, ensuring optimal RF performance is achieved early in the fabrication sequence.
2Reliability
If gate contacts are placed closer to gate stack ends, then gate resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The gate contact formation process is segmented into distinct stages: lateral extension to reach gate stack ends, followed by separate metallization filling. This segmentation allows each step to be optimized independently, reducing the precision burden on any single process while achieving the overall goal of low gate resistance.
Solution Approach 2:
The patent uses an intermediary lateral extension structure that bridges the gap between the simplified STI-region contact approach and the ideal end-contact configuration. This intermediary structure enables gradual transition to low-resistance contact without requiring ultra-precise single-step placement.
3Productivity
If IC structures are scaled down, then circuit density increases, but gate resistance increases
Solution Approach 1:
The patent applies local quality by extending the gate contact laterally only in the regions adjacent to the gate stack ends, while maintaining compact dimensions in other areas. This localized extension reduces gate resistance specifically where it matters most for RF performance without increasing overall device footprint, enabling continued scaling.
Solution Approach 2:
The lateral gate contact extension is nested within the existing gate stack structure, utilizing the vertical space and lateral footprint already defined by the gate stack. This nesting approach allows reduced gate resistance without adding external dimensions that would limit further scaling.
Data Source
AI summary
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; an upper conductor extending above, without contacting, the source/drain contact, wherein the upper conductor extends within the dielectric layer to contact the gate conductor within the gate stack.