Gate Contact and Via Plug Layout for Low-Capacitance Semiconductors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in reducing capacitance between contacts and ensuring electrical stability as pitch sizes decrease, while also requiring simplified fabrication processes to lower costs.
Innovation Solution
A semiconductor device design featuring a gate structure with a gate electrode and gate spacer, where the gate contact and via plug are made of single-grain tungsten, and are formed simultaneously with different aspect ratios to share the same upper surface plane but have distinct lower surface heights, simplifying the fabrication process and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pitch size is reduced to increase device density, then device density is improved, but capacitance between contacts increases and electrical stability deteriorates
Solution Approach 1:
The patent transitions from conventional planar contacts to three-dimensional vertically-aligned contact structures (gate contact and via plug) that extend through multiple interlayer insulating films. This vertical arrangement in the third dimension allows contacts to reach lower layers without increasing lateral pitch, maintaining electrical stability while preserving device density.
Solution Approach 2:
The gate contact and via plug are formed simultaneously in a single fabrication process step rather than sequentially. This merging of formation steps reduces process complexity and ensures consistent electrical properties, addressing reliability concerns while maintaining the compact vertical structure needed for high density.
2Reliability
If conventional multi-step fabrication process is used to ensure contact formation, then contact reliability is improved, but manufacturing complexity increases and cost increases
Solution Approach 1:
The gate contact hole and via hole are formed simultaneously through a single etching and filling process rather than sequentially. This consolidation maintains contact reliability by ensuring proper formation of both structures in one operation while significantly reducing fabrication process complexity and manufacturing cost.
Solution Approach 2:
The contact formation process is designed to serve multiple functions simultaneously: forming both gate contacts and via plugs, creating vertically-aligned structures, and establishing electrical connections to different layers all in one operation. This multi-functionality reduces overall process complexity while maintaining reliability.
Data Source
AI summary
A semiconductor device may include an active pattern extending in a first direction, a gate structure which is placed on the active pattern to be spaced apart from each other in the first direction, and includes a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction, a gate contact on the gate structure, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a via plug on the source/drain contact. An upper surface of the gate contact and a second upper surface of the via plug may be placed on the same plane. A lower surface of the gate contact and a lower surface of the via plug may be different in height, on the basis of an upper surface of the active pattern.